Field-effect transistor
A field-effect transistor (FET) in which a gate electrode is located between a source electrode formed on one side of the gate electrode and a drain electrode formed on the other side, a source ohmic contact is formed under the source electrode and a drain ohmic contact is formed under the drain electrode. In the FET, the rise in the channel temperature is suppressed, the parasitic capacitance with a substrate is decreased, and the temperature dependence of drain efficiency is reduced, so that highly efficient operation can be achieved at high temperatures. The drain electrode is divided into a plurality of drain sub-electrodes spaced from each other and an insulating region is formed between the drain ohmic contacts formed under the drain sub-electrodes.
1. A field-effect transistor disposed on a semiconductor layer, the field-effect transistor comprising:
a source electrode;
a source ohmic contact disposed under the source electrode and on the semiconductor layer;
a drain electrode divided into a plurality of drain sub-electrodes spaced from each other;
a plurality of drain ohmic contacts disposed under the drain sub-electrodes and on the semiconductor layer;
a gate electrode located between the source electrode disposed on one side of the gate electrode and the drain electrode disposed on the other side of the gate electrode,
wherein an insulating region is disposed between the drain ohmic contacts disposed under the drain sub-electrodes, the insulating region being disposed within the semiconductor layer.
2. The field-effect transistor according to claim 1 , wherein the semiconductor layer is disposed on a high-resistivity Si substrate having a resistivity of 1.0×10 2 Ωcm or more at room temperature.
3. The field-effect transistor according to claim 1 , wherein the semiconductor layer is disposed on a low-resistivity Si substrate having a resistivity of 1.0×10 −1 Ωcm or less at room temperature.
4. The field-effect transistor according to claim 1 , wherein the semiconductor layer comprises a GaN layer, and the semiconductor layer is formed on a Si substrate.
5. The field-effect transistor according to claim 1 , wherein the semiconductor layer comprises a GaN layer and an AlGaN layer, and the semiconductor layer is formed on a Si substrate.
6. The field-effect transistor according to claim 1 , wherein the semiconductor layer comprises a layer structure of an AlGaN layer on a GaN layer, and the insulating region extends from an upper surface of the AlGaN layer to an upper side of the GaN layer.
7. A semiconductor device, comprising:
a semiconductor layer;
a field-effect transistor, comprising
a source electrode,
a source ohmic contact disposed under the source electrode and on the semiconductor layer,
a drain electrode divided into a plurality of drain sub-electrodes spaced from each other,
a plurality of drain ohmic contacts disposed under the drain sub-electrodes and on the semiconductor layer, and
a gate electrode located between the source electrode disposed on one side of the gate electrode and the drain electrode disposed on the other side of the gate electrode; and
an insulating region disposed only between the drain ohmic contacts formed under the drain sub-electrodes, the insulating region being disposed within the semiconductor layer.
8. The semiconductor device according to claim 7 , wherein the semiconductor layer is disposed on a high-resistivity Si substrate having a resistivity of 1.0×10 2 Ωcm or more at room temperature.
9. The semiconductor device according to claim 7 , wherein the semiconductor layer is disposed on a low-resistivity Si substrate having a resistivity of 1.0×10 −1 Ωcm or less at room temperature.
10. The semiconductor device according to claim 7 , wherein the semiconductor layer comprises a GaN layer, and the semiconductor layer is formed on a Si substrate.
11. The semiconductor device according to claim 7 , wherein the semiconductor layer comprises a GaN layer and an AlGaN layer, and the semiconductor layer is formed on a Si substrate.
12. The semiconductor device according to claim 7 , wherein the semiconductor layer comprises a layer structure of an AlGaN layer on a GaN layer, and the insulating region extends from an upper surface of the AlGaN layer to an upper side of the GaN layer.