Methods and apparatuses for generating network test packets and parts of network test packets

1. An apparatus that divides roles in generating test packets for high packet volume tests between a general purpose processor and a configurable logic device, including:

a microprocessor with a first memory;

a programmable logic device with a second memory, wherein the programmable logic device is coupled to the first memory by at least a local bus, the programmable logic device having configurable interconnections;

a physical port dispatching the test packets from the apparatus;

wherein the microprocessor comprises:

circuitry that generates a list of test packet recipes and test packet ingredients, and stores the list in the first memory for a particular test; and

circuitry that generates the test packet ingredients and the test packet recipes for a particular test, and stores the test packet ingredients and the test packet recipes in the first memory;

wherein the programmable logic device comprises:

circuitry that retrieves the list via at least the local bus into the second memory;

circuitry that retrieves the test packet ingredients and the test packet recipes according to the list, via at least the local bus into the second memory, in segments such that the second memory is not overflowed;

circuitry that generates test packets that combine the test packet ingredients according to the test packet recipes ongoing with the microprocessor generating the test packet ingredients for the particular test, and adding timestamps; and

circuitry that dispatches the test packets via the physical port according to the timestamps.

2. The apparatus of claim 1 , wherein the local bus supports access of the first memory by the programmable logic device at memory addresses specified by the programmable logic device.

3. The apparatus of claim 1 , wherein the test packets emulate network traffic from an emulated network.

4. The apparatus of claim 1 , wherein the programmable logic device retrieves the test packet ingredients and the test packet recipes via addresses in the first memory specified in the list.

5. The apparatus of claim 1 , wherein the test packet ingredients include a fill pattern indicator, and the programmable logic device is configured to add a fill pattern identified by the fill pattern indicator to the test packets.

6. A method communicating test packets with a network that divides roles in generating test packets for high packet volume tests between a general purpose processor and a configurable logic device, comprising:

generating, with a microprocessor, a list of test packet recipes and test packet ingredients, and storing the list in a first memory of the microprocessor for a particular test;

generating, with the microprocessor, the test packet ingredients and the test packet recipes for the particular test, and storing the test packet ingredients and the test packet recipes in the first memory;

retrieving with a programmable logic device having configurable interconnections and via at least a local bus, the list into a second memory of the programmable logic device;

retrieving with the programmable logic device and via at least the local bus into the second memory, the test packet ingredients and the test packet recipes according to the list, in segments such that the second memory is not overflowed;

generating with the programmable logic device, test packets that combine the test packet ingredients according to the test packet recipes, ongoing with the microprocessor generating the test packet ingredients for the particular test, and adding timestamps; and

dispatching from the programmable logic device, the test packets via a physical port according to the timestamps.