Multiprocessor system-on-a-chip for machine vision algorithms

1. A multiprocessor system, comprising:

a main memory;

multiple processing cores, which are configured to execute software that uses data stored in the main memory;

a data streaming unit, which is connected between the processing cores and the main memory so as to serve the multiple processing cores and is configured to pre-fetch the data from the main memory for use by the multiple processing cores while arbitrating between simultaneous memory accesses that are performed on behalf of two or more of the processing cores; and

a respective local memory associated with each processing core and configured to maintain, in a circular buffer, a respective list of addresses in the main memory from which the data for the processing core is to be pre-fetched,

wherein the circular buffer comprises a read pointer indicating a first location in the local memory into which the data streaming unit is to write the data from the main memory, and a write pointer indicating a second location in the local memory from which the data streaming unit is to write the data to the main memory, and is configured so that when the read pointer reaches the write pointer, further fetching of the data is suspended until the write pointer has advanced.

2. The multiprocessor system according to claim 1 , wherein the data streaming unit is configured to store the data in the main memory on behalf of the multiple processing cores.

3. The multiprocessor system according to claim 1 , wherein the data streaming unit comprises, for each processing core, a respective front-end unit that is configured to receive from the processing core the respective list of addresses in the main memory, and to pre-fetch the data from the main memory in accordance with the list.

4. The multiprocessor system according to claim 3 , wherein each processing core and the corresponding front-end unit are configured to exchange the data via the respective local memory.

5. The multiprocessor system according to claim 1 , wherein at least the processing cores and the data streaming unit are comprised in a single integrated circuit.

6. The multiprocessor system according to claim 1 , wherein the circular buffer comprises a current element pointer, which is advanced by the processing core to indicate a next location in the respective local memory from which the processing core is to read the data.

7. The multiprocessor system according to claim 6 , wherein when the current element pointer reaches the read pointer, the processing core is stalled until new data arrives.

8. A multiprocessor system, comprising:

a main memory;

multiple processing cores, which are configured to execute software that uses data stored in the main memory; and

a scratch-pad processing unit, which is connected to the processing cores and is configured to execute, on behalf of the multiple processing cores, a selected part of the software that causes two or more of the processing cores to access concurrently a given item of data,

wherein the scratch-pad processing unit comprises:

a dedicated memory for storing the given item of data that is accessed by the two or more of the processing cores; and

a scratch-pad controller, which is configured to accept scratch-pad instructions from the multiple processing cores and to execute the accepted scratch-pad instructions in the dedicated memory without physically locking the dedicated memory,

wherein the scratch-pad controller comprises:

an arbiter, which is configured to arbitrate the scratch-pad instructions accepted from the multiple processing cores in a rotating priority scheme;

read, execute and write stages arranged in order in a pipeline so as to execute the scratch-pad instructions provided by the arbiter according to the rotating priority scheme;

a comparator coupled to compare respective memory addresses of the scratch-pad instructions in the read and write stages; and

a multiplexer, which is configured to route data from the write stage back to the execute stage when the respective memory addresses are identical.

9. The multiprocessor system according to claim 8 , wherein at least the processing cores and the scratch-pad processing unit are comprised in a single integrated circuit.

10. A method for data processing, comprising:

executing software, which uses data stored in a main memory, on multiple processing cores of a multiprocessor system;

pre-fetching the data from the main memory by a data streaming unit that is connected, so as to serve the multiple processing cores, between the processing cores and the main memory, for use by the multiple processing cores, while arbitrating between simultaneous memory accesses that are performed on behalf of two or more of the processing cores; and

maintaining, in a circular buffer in a respective local memory associated with each processing core, a respective list of addresses in the main memory from which the data for the processing core is to be pre-fetched,

wherein the circular buffer comprises a read pointer indicating a first location in the local memory into which the data streaming unit is to write the data from the main memory, and a write pointer indicating a second location in the local memory from which the data streaming unit is to write the data to the main memory, and is configured so that when the read pointer reaches the write pointer, further fetching of the data is suspended until the write pointer has advanced.

11. The method according to claim 10 , and comprising storing the data in the main memory on behalf of the multiple processing cores by the data streaming unit.

12. The method according to claim 10 , wherein pre-fetching the data comprises providing the respective list of addresses in the main memory from each processing core to a respective front-end unit, and pre-fetching the data from the main memory by the front-end unit in accordance with the list.

13. The method according to claim 12 , wherein pre-fetching the data comprises exchanging the data between each processing core and the respective front-end unit via the respective local memory that is associated with the processing core.

14. The method according to claim 10 , wherein at least the processing cores and the data streaming unit are comprised in a single integrated circuit.

15. A method for data processing, comprising:

executing software, which uses data stored in a main memory, on multiple processing cores of a multiprocessor system; and

using a scratch-pad processing unit that is connected to the multiple processing cores, executing on behalf of the processing cores a selected part of the software that causes two or more of the processing cores to access concurrently a given item of data,

wherein the scratch-pad processing unit comprises:

a dedicated memory for storing the given item of data that is accessed by the two or more of the processing cores; and

a scratch-pad controller, which is configured to accept scratch-pad instructions from the multiple processing cores and to execute the accepted scratch-pad instructions in the dedicated memory without physically locking the dedicated memory,

wherein the scratch-pad controller comprises:

an arbiter, which is configured to arbitrate the scratch-pad instructions accepted from the multiple processing cores in a rotating priority scheme;

read, execute and write stages arranged in order in a pipeline so as to execute the scratch-pad instructions provided by the arbiter according to the rotating priority scheme;

a comparator coupled to compare respective memory addresses of the scratch-pad instructions in the read and write stages; and

a multiplexer, which is configured to route data from the write stage back to the execute stage when the respective memory addresses are identical.

16. The method according to claim 15 , wherein at least the processing cores and the scratch-pad processing unit are comprised in a single integrated circuit.