System and process for packet delineation
View Patent ↗An error management system and process can be used to identify an erroneous data packet in a data stream. In response to identifying the erroneous data packet, a subsequent valid data packet is located in the data stream. In one embodiment, a plurality of candidate locations of header checksum windows are searched and checked for a valid checksum. Multiple integrity checks of multiple header checksums can be used to reduce the probability of a false positive integrity check. In another embodiment, one or more information data fields can used for determining packet integrity by determining if the fields contain valid information bits.
1. A communication apparatus to process a data stream comprising an allocation block having a known length, the allocation block comprising a plurality of variable length packet data units (PDUs), the apparatus comprising:
a memory device; and
a processor configured to communicate with the memory device, the processor further configured to identify an encoded checksum based on at least a portion of a first packet, wherein the first packet comprises a header having a packet length field and the encoded checksum is based on at least a portion of the header, to calculate a second checksum based on the at least the portion of the header of the first packet, to determine an integrity of the first packet by determining the first packet to be erroneous if the second checksum does not match the encoded checksum, and in response to determining the integrity of the first packet to be erroneous:
to identify a second packet at a location indicated by the packet length field of the first packet:
to determine that the packet length field of the first packet is correct on a condition that the second packet is identified at the location indicated by the packet length field of the first packet; and
to process the first packet as not erroneous on a condition that the packet length field of the first packet is determined to be correct.
2. The communication apparatus of claim 1 , wherein the variable length packets are contained in a data block having a known length.
3. The communication apparatus of claim 2 , wherein the data block having a known length corresponds to an allocation region of an orthogonal frequency division multiple access (OFDMA) system.
4. The communication apparatus of claim 1 , wherein the processor is further configured to determine multiple candidate locations in a header of a packet other than the first packet, to identify a first candidate encoded checksum for each of the multiple locations, and to calculate a second candidate checksum for each of the multiple locations based on a portion of the header of the packet other than the first packet that the encoded checksum is based on.
5. The communication apparatus of claim 4 , wherein identifying the second packet at the location indicated by the packet length field of the first packet comprises identifying a location of a header of the second packet that results in the calculated second candidate checksum matching the identified first candidate encoded checksum.
6. The communication apparatus of claim 1 , wherein in response to determining the integrity of the first packet to be erroneous, the processor is further configured to determine that the packet length field of the first packet is erroneous, to correct the packet length field, to calculate a third checksum for the packet header using the corrected packet length field, and to discard the first packet if the third checksum does not match the encoded checksum.