Method and apparatus for digital I/O expander chip with multi-function timer cells
A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a master counter. The status of the match registers can be retrieved through ports. The master counter is reloaded on rollover by a count limit register. The master counter has increment/decrement control and the rollover can be used in an interrupt control block to generate an interrupt request.
1. A method comprising:
loading a count limit register with a count limit;
generating a rollover signal when a master counter reaches a pre-specified count;
reloading said master counter with said count limit when said rollover signal occurs;
loading a plurality of match reload registers with values;
reloading a plurality of match registers with said values when said rollover signal occurs; and
generating one or more outputs when a master counter count and a match register value are equal.
2. The method of claim 1 further comprising controlling said master counter count via a direction control signal.
3. The method of claim 2 further comprising sending said one or more outputs to a interrupt control logic block.
4. The method of claim 3 further comprising generating an interrupt signal based on an N th event, wherein N is an integer greater than one.
5. An apparatus comprising:
means for loading a count limit register with a count limit;
means for generating a rollover signal when a master counter reaches a pre-specified count;
means for reloading said master counter with said count limit when said rollover signal occurs;
means for loading a plurality of match reload registers with values;
means for reloading a plurality of match registers with said values when said rollover signal occurs; and
means for generating one or more outputs when a master counter count and a match register value are equal.