IP Library Patent Application 13075132
Patent Application
App. No. 13/075,132

DATA STORAGE SYSTEM WITH SELF-SERVO-WRITING AND METHOD OF OPERATION THEREOF

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
13/075,132
Abstract

A method of operation of a data storage system includes: providing a disk having a reference servo; and positioning a read/write head over the disk with the reference servo including: collecting a raw phase error, estimating a phase delay error, estimating an estimated written-in error with the phase delay error subtracted from the raw phase error, calculating a remaining error based on the estimated written-in error, and adjusting a self-servo-writing clock based on the remaining error.

Claims (64)

1 . A method of operation of a data storage system comprising:

providing a disk having a reference servo; and

positioning a read/write head over the disk with the reference servo including:

collecting a raw phase error,

estimating a phase delay error,

estimating an estimated written-in error with the phase delay error subtracted from the raw phase error,

calculating a remaining error based on the estimated written-in error, and

adjusting a self-servo-writing clock based on the remaining error.

2 . The method as claimed in claim 1 wherein estimating the phase delay error includes estimating the phase delay error using statistical approach.

3 . The method as claimed in claim 1 further comprising:

calculating an actual phase error based on the self-servo-writing clock; and

wherein:

calculating the remaining error includes calculating the remaining error with the estimated written-in error subtracted from the actual phase error.

4 . The method as claimed in claim 1 further comprising generating a self-servo-writing timestamp with the self-servo-writing clock.

5 . The method as claimed in claim 1 further comprising generating a command based on the remaining error.

6 . A method of operation of a data storage system comprising:

providing a disk having a reference servo; and

positioning a read/write head over the disk with the reference servo including:

generating a nominal timestamp,

collecting a raw phase error,

estimating a phase delay error,

estimating an estimated written-in error with the phase delay error subtracted from the raw phase error,

calculating a remaining error based on the estimated written-in error, and

adjusting a self-servo-writing clock based on the remaining error.

7 . The method as claimed in claim 6 wherein estimating the phase delay error includes estimating the phase delay error using linear regression.

8 . The method as claimed in claim 6 further comprising:

calculating an actual phase error based on the self-servo-writing clock and the nominal timestamp; and

wherein:

calculating the remaining error includes calculating the remaining error with the estimated written-in error subtracted from the actual phase error.

9 . The method as claimed in claim 6 further comprising:

generating a self-servo-writing timestamp with the self-servo-writing clock; and

calculating an actual phase error as a difference between the self-servo-writing timestamp and the nominal timestamp.

10 . The method as claimed in claim 6 further comprising:

generating a command based on the remaining error; and

wherein:

adjusting the self-servo-writing clock includes adjusting the self-servo-writing clock based on the command.

11 . A data storage system comprising:

a disk having a reference servo;

a read/write head coupled to and positioned over the disk with the reference servo;

a collect error module, coupled to the read/write head, for collecting a raw phase error;

a phase delay detection module, coupled to the collect error module, for estimating a phase delay error;

a phase anticipation detection module, coupled to the phase delay detection module, for estimating an estimated written-in error with the phase delay error subtracted from the raw phase error;

an error subtraction unit, coupled to the phase anticipation detection module, for calculating a remaining error based on the estimated written-in error; and

a voltage controlled oscillator, coupled to the error subtraction unit, for adjusting a self-servo-writing clock based on the remaining error.

12 . The system as claimed in claim 11 wherein the phase delay detection module is for estimating the phase delay error using statistical approach.

13 . The system as claimed in claim 11 further comprising:

a timestamp subtraction unit, coupled to the voltage controlled oscillator, for calculating an actual phase error based on the self-servo-writing clock; and

wherein:

the error subtraction unit is for calculating the remaining error with the estimated written-in error subtracted from the actual phase error.

14 . The system as claimed in claim 11 further comprising a free-running counter, coupled to the voltage controlled oscillator, for generating a self-servo-writing timestamp with the self-servo-writing clock.

15 . The system as claimed in claim 11 further comprising a controller, coupled to the error subtraction unit, for generating a command based on the remaining error.

16 . The system as claimed in claim 11 further comprising a nominal timestamp generation unit for generating a nominal timestamp.

17 . The system as claimed in claim 16 wherein the phase delay detection module is for estimating the phase delay error using linear regression.

18 . The system as claimed in claim 16 further comprising:

a timestamp subtraction unit, coupled to the nominal timestamp generation unit, for calculating an actual phase error based on the self-servo-writing clock and the nominal timestamp; and

wherein:

the error subtraction unit is for calculating the remaining error with the estimated written-in error subtracted from the actual phase error.

19 . The system as claimed in claim 16 further comprising:

a free-running counter, coupled to the voltage controlled oscillator, for generating a self-servo-writing timestamp with the self-servo-writing clock; and

a timestamp subtraction unit, coupled to the free-running counter, for calculating an actual phase error as a difference between the self-servo-writing timestamp and the nominal timestamp.

20 . The system as claimed in claim 16 further comprising:

a controller, coupled to the error subtraction unit, for generating a command based on the remaining error; and

wherein:

the voltage controlled oscillator is for adjusting the self-servo-writing clock based on the command.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SEAGATE TECHNOLOGY INTERNATIONAL
Reel/Frame 028085/0220 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2011
From: WANG, ZHI; NGUYEN, TUNG H.; KIM, GLENN G.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 026045/0043 →