IP Library Granted Patent US 8,743,967
Granted Patent B2
US 8,743,967 · App. 13/076,554 · Granted Jun 3, 2014

Multi-format video decoder with vector processing instructions and methods for use therewith

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Quick Facts
Patent No.
US 8,743,967
App. No.
13/076,554
Granted
Jun 3, 2014
Kind
B2
Abstract

A video decoder includes an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal. A multi-format video decoding device includes a plurality of vector processor units that generate a decoded video signal from the EDC data. The plurality of vector processing units are programmed via VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion.

Claims (17)

1. A video decoder comprising:

an entropy decoding device that generates entropy decoded (EDC) data from an encoded video signal;

a multi-format video decoding device, coupled to the entropy decoding device, includes a plurality of vector processor units for generating a decoded video signal from the EDC data, wherein the plurality of vector processing units are programmed via VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion, and wherein the scalar instruction portion includes non-vector data and a non-vector processing command to be executed by the at least one of the plurality of vector processing units and wherein the non-vector processing command includes at least one of: a scalar logical operation on the non-vector data, and a scalar arithmetic operation on the non-vector data.

2. The video decoder of claim 1 wherein the plurality of vector processing units includes at least one matrix vector processor that parallel processes at least one matrix operation of the multi-format video decoding device, and wherein the vector instruction includes a matrix command and matrix data.

3. The video decoder of claim 1 wherein the plurality of vector processors includes at least one filter vector processor that parallel processes at least one filter operation of the multi-format video decoding device and wherein the vector instruction includes a filter command and filter data.

4. The video decoder of claim 1 wherein the branching instruction includes at least one of: an unconditional branching instruction, and a conditional branching instruction.

5. The video decoder of claim 1 wherein the non-vector processing command is executed in a single instruction of the at least one of the plurality of vector processing units.

6. The video decoder of claim 1 wherein the encoded video signal is encoded in accordance with a VP8 coding standard.

7. A method comprising:

generating entropy decoded (EDC) data from an encoded video signal;

programming a plurality of vector processor units, based on VPU instructions formatted to include a vector instruction portion, a scalar instruction portion, and a branching instruction portion, wherein the scalar instruction portion includes non-vector data and a non-vector processing command to be executed by the at least one of the plurality of vector processor units and wherein the non-vector processing command includes at least one of: a scalar logical operation on the non-vector data, and a scalar arithmetic operation on the non-vector data; and

generating a decoded video signal from the EDC data, via the plurality of vector processing units.

8. The method of claim 7 wherein programming the plurality of vector processor units includes configuring at least one matrix vector processor to parallel process at least one matrix operation, and wherein the vector instruction includes a matrix command and matrix data.

9. The method of claim 7 wherein programming the plurality of vector processor units includes configuring at least one filter vector processor to parallel process at least one filter operation, and wherein the vector instruction includes a filter command and filter data.

10. The method of claim 7 wherein the branching instruction includes at least one of: an unconditional branching instruction, and a conditional branching instruction.

11. The method of claim 7 wherein the non-vector processing command is executed in a single instruction of the at least one of the plurality of vector processing units.

12. The method of claim 7 wherein the encoded video signal is encoded in accordance with a VP8 coding standard.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Jul 6, 2023
From: COMERICA BANK
To: VIXS SYSTEMS, INC.
Reel/Frame 064224/0885 →
SECURITY INTEREST Recorded Jul 18, 2016
From: VIXS SYSTEMS INC.
To: COMERICA BANK
Reel/Frame 039380/0479 →