Method for planar implementation of π/8 gate in chiral topological superconductors
View Patent ↗Disclosed herein is a topologically protected π/8-gate which becomes universal when combined with the gates available through quasi-particle braiding and planar quasi-particle interferometry. A twisted interferometer, and a planar π/8-gate in CTS, implemented with the help of the twisted interferometer, are disclosed. Embodiments are described in the context of state X (CTS) supported by an ISH, although the concept of a twisted-interferometer is more general and has relevance to all anionic, i.e. quasiparticle systems.
1. A twisted interferometer, comprising:
a source, a first drain, and a second drain;
a first tunneling path between a first vacuum and a second vacuum;
a second tunneling path between the first vacuum and a third vacuum; and
a third tunneling path between the second vacuum and the third vacuum,
wherein a voltage bias is maintained between the source and the drains such that a current flows around edges of the vacuums.
2. The interferometer of claim 1 , wherein each of the vacuums is an absence of X-state fluid or a transformed fluid without non-Abelian properties, and the vacuum is created by electronic or magnetic top gating.
3. The interferometer of claim 1 , wherein a first distance through the first and third tunneling paths between a first point on an edge of the first vacuum and a third point on an edge of the third vacuum is approximately ⅕ of a second distance through the second tunneling path between the first point and the third point.
4. The interferometer of claim 3 , wherein the first distance is measured around an edge of the second vacuum, and the second distance is measured around an edge of the first vacuum and an edge of the third vacuum.
5. The interferometer of claim 1 , wherein tunneling is allowed at each of the tunneling paths for an interval of time that is proportional to the time for a wave packet to propagate once around the second vacuum at group velocity.
6. The interferometer of claim 1 , wherein, while the first, second, and third tunneling junctions are open, all current flows into the first drain.
7. The interferometer of claim 1 , wherein a wave packet of σ-particles with support small with respect to the first distance is allowed to transit to the second vacuum with a first amplitude.
8. The interferometer of claim 7 , wherein the wave packet is allowed to transit the first vacuum with a second amplitude that is smaller than the first amplitude.
9. The interferometer of claim 8 , wherein a second wave packet arrives at the second tunneling junction such that the packet is transmitted with a third amplitude.
10. The interferometer of claim 9 , wherein the first wave packet arrives at the third tunneling junction precisely when the second wave packet also arrives at the third tunneling junction.
11. The interferometer of claim 10 , wherein the first wave packet arrives at the third tunneling junction after 2.5 trips around the second vacuum.
12. The interferometer of claim 11 , wherein the third tunneling path is briefly made substantial such that the two wave packets interfere.
13. The interferometer of claim 12 , wherein the nature of the interference is detected at the second drain.
14. A planar π/8-gate in a chiral topological superconductor, comprising a low mobility electronic structure comprising a spin-orbit coupled semiconductor, an ordinary superconductor, a ferro-magnetic insulator or a ferri-magnetic insulator.
15. The gate of claim 14 , wherein the electronic structure is capable of supporting universal topological, fault tolerant quantum computation.
16. A topologically protected method for implementing a π/8-gate in a chiral-topological-superconductor (CTS), Ising-sandwich-heterostructure (ISH) device, the method comprising:
implementing universal quantum computation in a topologically protected, fault-tolerant manner within the CTS-ISH device.
17. The method of claim 16 , wherein the CTS-ISH device comprises a low mobility electronic structure that is capable of supporting universal topological, fault tolerant quantum computation.
18. The method of claim 17 , wherein the low mobility electronic structure comprises a spin-orbit coupled semiconductor.
19. The method of claim 17 , wherein the low mobility electronic structure comprises an ordinary superconductor.
20. The method of claim 17 , wherein the low mobility electronic structure comprises a ferro- or ferri-magnetic insulator.