IP Library Granted Patent US 8,989,263
Granted Patent B2
US 8,989,263 · App. 13/079,978 · Granted Mar 24, 2015

Inverse quantizer supporting multiple decoding processes

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Quick Facts
Patent No.
US 8,989,263
App. No.
13/079,978
Granted
Mar 24, 2015
Kind
B2
Abstract

The present invention provides an apparatus for performing inverse quantization for multiple decoding standards, where the functional operations that comprise the inverse quantizer are modularly implemented and can be selectably performed. Each operation can be represented via a table entry in an associated memory area, with the functional operation being performed via reference to that table entry. Functional operations can be bypassed as needed if inverse quantization does not need to be performed on a set of data. Certain other processing operations can be performed between steps as needed to accommodate different coding standards. Macroblock data can be read from and written back to a common storage area, or a direct path is provided for writing the data directly to a subsequent inverse transform device.

Claims (35)

1. An inverse quantizer apparatus for processing macroblocks of data, the apparatus having modular operation elements that can be invoked via associated inverse quantizer commands in order to accommodate different coding standards, the apparatus comprising:

a memory area having an input buffer interface and an output buffer interface, for storing command data, macroblock header data, and associated block coding data;

a run level decoder device;

an inverse scan pattern device;

a reorder RAM device; and

an inverse quantizer command and macroblock header decoder device configured to receive the command data, macroblock header data, and associated block coding data from the memory area, the inverse quantizer command and macroblock header decoder device further configured to decode the command data, the macroblock header data, and the associated block coding data, and transmit decoded parameters and control information to the run level decoder device, the inverse scan pattern device, and the reorder RAM device.

2. The inverse quantizer apparatus of claim 1 , further comprising a DMA/Bridge interface for transferring data between the memory area and one or more of the inverse quantizer command and macroblock header decoder device, the run level decoder device, the inverse scan pattern device, or the reorder RAM device.

3. The inverse quantizer apparatus of claim 2 , wherein an inverse quantizer result is read from and stored back into the same macroblock buffer associated with the memory area.

4. The inverse quantizer apparatus of claim 1 , wherein an inverse quantizer command is read from a direct command register or from the memory area.

5. The inverse quantizer apparatus of claim 1 , further comprising an inverse quantizer start command address register updated to begin the inverse quantizer operation.

6. The inverse quantizer apparatus of claim 1 , further comprising a Q-matrix storage device operatively coupled between the inverse scan pattern device and at least one other device and broken down into addressable storage areas for different functional Q-matrix data.

7. The inverse quantizer apparatus of claim 1 , further comprising a Q-scale storage device operatively coupled between the inverse scan pattern device and at least one other device and broken down into addressable storage areas for different functional Q-scale data.

8. An inverse quantizer apparatus comprising:

a run level decoder device;

an inverse scan pattern device;

a reorder RAM device; and

an inverse quantizer command and macroblock header decoder device configured to receive command data, macroblock header data, and associated block coding data from a memory area, the inverse quantizer command and macroblock header decoder device further configured to decode the command data, the macroblock header data, and the associated block coding data and transmit decoded parameters and control information to the run level decoder device, the inverse scan pattern device, and the reorder RAM device;

wherein the run level decoder device is configured to determine whether to perform run level decoding based on the control information received from the inverse quantizer command and macroblock header decoder device;

wherein the inverse scan pattern device is configured to determine whether to perform inverse scan decoding based on the control information received from the inverse quantizer command and macroblock header decoder device; and

wherein the reorder RAM device is configured to perform inverse scan reordering based on the parameters received from the received from the inverse quantizer command and macroblock header decoder device.

9. The inverse quantizer apparatus of claim 8 , further comprising a data packing device positioned after the reorder RAM for arranging output data into an output buffer of the memory area.

10. The inverse quantizer apparatus of claim 9 , wherein a direct path is provided from the reorder RAM device to an inverse transform apparatus associated with the inverse quantizer apparatus.

11. The inverse quantizer apparatus of claim 8 , the inverse quantizer apparatus having modular operation elements that can be invoked via associated inverse quantizer commands in order to accommodate different coding standards, wherein one or more modular operation elements can be selectively bypassed.

12. A method comprising:

receiving, at a command and macroblock header decoder device of an inverse quantizer device, command data, macroblock header data, and block coding data from a memory area;

decoding, using the command and macroblock header decoder device, the command data, macroblock header data, and block coding data received from the memory area to generate decoded control and parameter information; and

transmitting the decoded parameters and control information from the command and macroblock header decoder device to a run level decoder device, an inverse scan pattern device, and a recorder RAM device of the inverse quantizer device, the run level decoder device configured to determine whether to perform run level decoding based on the decoded control and parameter information, the inverse scan pattern device configured to determine whether to perform inverse scan decoding based on the decoded control and parameter information, and the reorder RAM device configured to perform inverse scan reordering based on the decoded control and parameter information.

13. The method of claim 12 , the step of receiving the command data, macroblock header data, and block coding data comprising receiving the command data, macroblock header data, and block coding data at the command and macroblock header decoder device from the memory area via a DMA/Bridge interface.

14. The method of claim 13 , further comprising reading a result from and storing the result back into a same macroblock buffer associated with the memory area.

15. The method of claim 12 , the step of receiving the command data, macroblock header data, and block coding data comprising reading an inverse quantizer command from a direct command register or from the memory area.

16. The method of claim 12 , further comprising beginning an inverse quantizer operation based on an update of an inverse quantizer start command address register.

17. The method of claim 12 , further comprising storing a plurality of different functional Q-matrix data items within different addressable storage areas of a Q-matrix storage device.

18. The method of claim 12 , further comprising storing a plurality of different functional Q-scale data items within different addressable storage areas of a Q-scale storage device.

19. The method of claim 12 , further comprising positioning a data packing device after the reorder RAM for arranging output data into an output buffer of the memory area.

20. The method of claim 12 , the inverse quantizer apparatus having modular operation elements that can be invoked via associated inverse quantizer commands in order to accommodate different coding standards, the method further comprising selectively bypassing one or more of the modular operation elements.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
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TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
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To: BROADCOM CORPORATION
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
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PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2014
From: HSIUN, VIVIAN; MACINNIS, ALEXANDER G.; XIE, XIAODONG
To: BROADCOM CORPORATION
Reel/Frame 033731/0484 →