Low jitter clock interpolator

1. A low jitter clock interpolator circuit, comprising:

a time based numerically controlled oscillator (NCO) configured to produce a NCO output in response to a high speed clock (hsclk) input and a frequency control word (FCW), where the output periods of the NCO output are integer multiples of the hsclk period and the average output period of the NCO output corresponds to the FCW;

a clock interpolator circuit configured to receive the NCO output and the hsclk input and to generate a plurality of different phases of the NCO output; and

a phase calculator circuit configured to select phases generated by the clock interpolator to produce a low jitter clock signal output having an output period that corresponds to the FCW.

2. The low jitter clock interpolator circuit of claim 1 , wherein the jitter in the low jitter clock signal output is within the precision of the phases generated by the clock interpolator circuit.

3. The low jitter clock interpolator circuit of claim 1 , wherein:

a plurality of bits of the FCW are indicative of an integer part of the FCW;

a plurality of bits of the FCW are indicative of a fractional part of the FCW;

the time based NCO accumulates the fractional part of the FCW; and

the phase calculator circuit selects a phase generated by the clock interpolator circuit based upon the accumulated fractional part of the FCW.

4. The low jitter clock interpolator circuit of claim 3 , wherein the NCO comprises:

a first adder configured to add the bits corresponding to the factional part of the FCW to an accumulated value stored in a first buffer and to output the sum to the first buffer and to provide an overflow bit output in response to overflow of the first adder;

a second adder configured to sum the bits corresponding to the integer part of the FCW with the overflow bit output of the first adder and to provide the sum to a second buffer; and

a down counter configured to load the value from the second buffer, count down to 1 and generate a puke on the NCO output when the count equals 1.

5. The low jitter clock interpolator of claim 3 , wherein the clock interpolator circuit comprises:

a tapped delay line configured to receive the NCO output as an input; and

a multiplexer configured to select a tap from the tapped delay line as the low jitter clock signal output in response to an input received from the phase calculator circuit.

6. The low jitter clock interpolator of claim 5 , wherein the phase calculator circuit is configured to scale the accumulated fractional part of the FCW and to provide the result to the multiplexer to select a tap from the tapped delay line as the low jitter clock signal output.

7. The low jitter clock interpolator of claim 6 , wherein:

the tapped delay line includes a minimum number of taps so as to span at least one high speed clock period; and

the phase calculator circuit is configured to calibrate the gain so as to exclude at least one tap at the end of the delay line so that the delay of the remaining taps span a hsclk period.

8. The low jitter clock interpolator of claim 3 , wherein the clock interpolator circuit comprises:

a current starved delay line configured to receive the NCO output as an input, were the gains of the delays in the current starved delay line are controlled via a plurality of current digital to analog converters; and

a multiplexer configured to select a tap from the current starved delay line as the low jitter clock signal output in response to an input received from the phase calculator.

9. The low jitter clock interpolator of claim 8 , wherein the phase calculator circuit is configured to control the gains of the delays in the current starved delay line using the digital to analog converters and to provide the accumulated fractional part of the FCW to the multiplexer to select a tap from the tapped delay line as the low jitter clock signal output.

10. The low jitter clock interpolator of claim 9 , wherein the phase calculator circuit is configured to calibrate the gains of the delays in the current starved delay line so that the current starved delay line spans a single hsclk period.

11. A method of generating a low jitter clock output, comprising:

generating a clock output using a time based numerically controlled oscillator (NCO) in response to a high speed clock (hsclk) input and a frequency control word (FCW) input, where the output periods of the clock output are integer multiples of the hsclk period and the average output period of the clock output corresponds to the FCW;

interpolating the clock output using a clock interpolator circuit to produce a plurality of clock output phases; and

selecting clock output phases using a phase calculator circuit to produce a low jitter clock output having an output period that corresponds to the FCW.

12. The method of claim 11 , wherein:

generating a clock output using a time based NCO in response to the hsclk input and the FCW input further comprises:

accumulating a plurality of bits of the FCW that are indicative of a fractional part of the FCW in the NCO; and

selecting clock output phases using a phase calculator circuit to produce a low jitter clock output having an output period that corresponds to the FCW, further comprises:

selecting clock output phases from the clock interpolator using the phase calculator circuit based upon the accumulated fractional part of the FCW.

13. The method of claim 12 , wherein:

accumulating a plurality of bits of the FCW that are indicative of a fractional part of the FCW in the NCO comprises:

accumulating a fractional part of the FCW in a first buffer by adding the plurality of bits from the FCW control word corresponding to a fractional part of the FCW and the previous value in the first buffer; and

generating a clock output using a time based NCO in response to the hsclk input and the FCW input further comprises:

providing an overflow bit output to a second adder in response to an overflow of the first adder;

accumulating an integer part of the FCW in a second buffer by adding the plurality of bits from the FCW corresponding to the integer part of the FCW and the overflow bit output by the first adder using the second adder;

loading the value in the second buffer into a down counter circuit when a clock output puke is generated; and

counting down from the value loaded into the down counter circuit and generating a clock output puke when the count equals 1.

14. The method of claim 12 , wherein interpolating the clock output using a clock interpolator circuit to produce a plurality of clock output phases further comprises providing the clock output to a delay line having a plurality of delayed outputs.

15. The method of claim 14 , wherein selecting clock output phases from the clock interpolator using the phase calculator circuit based upon the accumulated fractional part of the FCW further comprises:

selecting one of the outputs of the delay line as the low jitter clock output using a multiplexer based upon the accumulated fractional part of the FCW.

16. The method of claim 15 , wherein the delay line is a tapped delay line.

17. The method of claim 16 , wherein the tapped delay line includes a minimum number of taps so as to span at least one high speed clock period.

18. The method of claim 15 , wherein selecting one of the outputs of the delay line as the low jitter clock output using a multiplexer based upon the accumulated fractional part of the FCW further comprises:

scaling the accumulated fractional part of the FCW by a gain factor using the phase calculator circuit; and

providing the scaled accumulated fractional part of the FCW to the multiplexer to select an output of the delay line.

19. The method of claim 18 , further comprising calibrating the gain factor so as to exclude at least one tap at the end of the delay line so that the delay of the remaining taps span a hsclk period.

20. The method of claim 15 , wherein the delay line is a current starved delay line.

21. The method of claim 20 , wherein selecting one of the outputs of the delay line as the low jitter clock output using a multiplexer based upon the accumulated fractional part of the FCW further comprises:

calibrating the gains of the delays in the current starved delay line using the phase calculator so that the current starved delay line spans one hsclk period; and

providing the accumulated fractional part of the FCW to the multiplexer to select an output of the delay line.