Method for producing a transistor gate with sub-photolithographic dimensions
View Patent ↗A method of fabricating a semiconductor device is disclosed. The method comprises patterning a photoresist over a compound semiconductor substrate; reducing a width of the photoresist; forming a hardmask over the substrate and not over the photoresist; removing the photoresist; etching to form and opening down to the substrate; forming a gate in the opening; and removing the hardmask except beneath the gate.
1. A method of fabricating a semiconductor device, the method comprising:
patterning a photoresist over a compound semiconductor substrate;
reducing a width of the photoresist;
forming a hardmask over the compound semiconductor substrate and not over the photoresist;
removing the photoresist;
etching to form an opening down to the compound semiconductor substrate;
forming a gate in the opening; and
removing the hardmask except beneath the gate.
2. A method as claimed in claim 1 , further comprising, before patterning the photoresist, forming a dielectric layer over the compound semiconductor substrate, wherein the opening is formed through the dielectric layer.
3. A method as claimed in claim 2 , further comprising, removing the dielectric over the compound semiconductor substrate except in a region beneath a portion of the gate.
4. A method as claimed in claim 1 , wherein the etching to form an opening is an anisotropic etching.
5. A method as claimed in claim 1 , wherein the forming the gate comprises a lift-off process.
6. A method as claimed in claim 1 , wherein the forming the gate comprises a plating process.
7. A method as claimed in claim 1 , wherein the compound semiconductor substrate comprises a Group III-V semiconductor material.