IP Library › Patent Application 13085096
Patent Application
App. No. 13/085,096

Selective Optical Proximity Layout Design Data Correction

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Quick Facts
Patent No.
US None
App. No.
13/085,096
Abstract

After layout design data has been modified using an OPC process, a repair flow is initiated. This repair flow includes analyzing the modified data to identify any remaining or new potential print errors in the layout data. Regions then are formed around the identified potential print errors, and a subsequent OPC process is performed only on the data within these regions using a different set of process parameters from the process parameters employed by the initial OPC process. This repair flow is iteratively repeated, where a different set of process parameter values for the subsequent OPC process is used during each iteration.

Claims (36)

1 . A computer-implemented method of modifying integrated circuit layout design data, comprising:

A. identifying a layout design, the layout design representing at least a portion of an integrated circuit design;

B. implementing a resolution enhancement process having a first set of parameter values on the layout design, wherein an altered layout design is generated and wherein the altered layout design includes assist features;

C. checking for errors with the assist features within the altered layout design, wherein one or more errors is detected;

D. forming a re-correction region around at least one of the one or more detected errors, wherein the re-correction region designates a sub-portion of the altered layout design;

E. identifying a second set of parameter values, wherein the second set of parameter values is different than the first set of parameter values;

F. implementing a correction process having the second set of parameter values on the sub-portion of the altered layout design designated by the re-correction region, wherein an altered sub-portion of the layout design is generated;

G. stitching the altered sub-portion of the layout design into the altered layout design, wherein a modified layout design is generated; and

H. saving the modified layout design to a memory storage location.

2 . A computer-implemented method of modifying integrated circuit layout design data, comprising:

A. identifying a layout design, the layout design representing at least a portion of an integrated circuit design;

B. implementing a resolution enhancement process having a first set of parameter values on the layout design, wherein an altered layout design is generated;

C. checking for errors within the altered layout design, wherein one or more errors is detected;

D. forming a re-correction region around at least one of the one or more detected errors, wherein the re-correction region designates a sub-portion of the altered layout design;

E. identifying a second set of parameter values, wherein the second set of parameter values is different than the first set of parameter values;

F. implementing an inverse-lithography process having the second set of parameter values on the sub-portion of the altered layout design designated by the re-correction region, wherein an altered sub-portion of the layout design is generated;

G. stitching the altered sub-portion of the layout design into the altered layout design, wherein a modified layout design is generated; and

H. saving the modified layout design to a memory storage location.

3 . A computer-implemented method of modifying integrated circuit layout design data, comprising:

A. identifying a layout design, the layout design representing at least a portion of an integrated circuit design;

B. implementing a layout decomposition process having a first set of parameter values on the layout design, wherein an altered layout design is generated;

C. checking for errors within the altered layout design, wherein one or more errors is detected;

D. forming a re-correction region around at least one of the one or more detected errors, wherein the re-correction region designates a sub-portion of the altered layout design;

E. identifying a second set of parameter values, wherein the second set of parameter values is different than the first set of parameter values;

F. implementing a correction process having the second set of parameter values on the sub-portion of the altered layout design designated by the re-correction region, wherein an altered sub-portion of the layout design is generated;

G. stitching the altered sub-portion of the layout design into the altered layout design, wherein a modified layout design is generated; and

H. saving the modified layout design to a memory storage location.

4 . A computer-implemented method of modifying integrated circuit layout design data, comprising:

A. identifying a layout design, the layout design representing at least a portion of an integrated circuit design;

B. implementing a resolution enhancement process having a first set of parameter values on the layout design, wherein an altered layout design is generated;

C. designating one or more areas of the altered layout design;

D. forming a re-correction region around the designated areas, wherein the re-correction region designates a sub-portion of the altered layout design;

E. identifying a second set of parameter values, wherein the second set of parameter values is different than the first set of parameter values;

F. implementing a correction process having the second set of parameter values on the sub-portion of the altered layout design designated by the re-correction region, wherein an altered sub-portion of the layout design is generated;

G. stitching the altered sub-portion of the layout design into the altered layout design, wherein a modified layout design is generated; and

H. saving the modified layout design to a memory storage location.