Dual processor system and method for using the same

1. A dual processor system for electronic devices, comprising:

a first processor;

a second processor; and

a dual-ported random access memory (DPRAM) electrically connected to the first processor and the second processor; wherein when the first processor stores data to be processed by the second processor to the DPRAM and writes interrupt data to the DPRAM, the DPRAM generates a first information status; the second processor reads the interrupt data once when detecting the first information status, processes the to be processed data when successfully reading the interrupt data once, and reads the interrupt data twice when completing processing the to be processed data; the DPRAM generates a second information status when the second processor successfully reads the interrupt data twice, and the first processor identifies that the second processor has processed the to be processed data when detecting the second information status.

2. The dual processor system as claimed in claim 1 , wherein when the second processor stores data to be processed by the first processor to the DPRAM and writes the interrupt data to the DPRAM, the DPRAM generates the first information status; the first processor reads the interrupt data once when detecting the first information status, processes the to be processed data when successfully reading the interrupt data once, and reads the interrupt data twice when completing processing the to be processed data; the DPRAM generates the second information status when the first processor successfully reads the interrupt data twice, and the second processor identifies that the first processor has processed the to be processed data when detecting the second information status.

3. The dual processor as claimed in claim 2 , wherein the DPRAM includes a data area, two mailboxes, a configuration area, and two interrupt pins; when the first processor stores data to be processed by the second processor to the data area and writes interrupt data to the configuration area and one of the two mailboxes, the DPRAM generates the first information status on one of the two interrupt pins; the second processor reads the interrupt data stored in the configuration area when detecting the first information status on the one of the two interrupt pins, processes the data stored in the data area when successfully reading the interrupt data stored in the configuration area, and reads the interrupt data stored in the one of the two mailboxes when completing processing the data stored in data area; the DPRAM generates the second information status on the one of the two interrupt pins when the second processor successfully reads the interrupt data stored in the one of the two mailboxes, and the first processor identifies that the second processor has processed the data stored in the data area when detecting the second information status on the one of the two interrupt pins.

4. The dual processor system as claimed in claim 3 , wherein when the second processor stores data to be processed by the first processor to the data area and writes interrupt data to the configuration area and the other of the two mailboxes, the DPRAM generates the first information status on the other of the two interrupt pins; the first processor reads the interrupt data in the configuration area when detecting the first information status on the other of the two interrupt pins, processes the data stored in the data area when successfully reading the interrupt data stored in the configuration area, and reads the interrupt data stored in the other of the two mailboxes when completing processing the data stored in data area; the DPRAM generates the second information status on the other of the two interrupt pins when the first processor successfully reads the interrupt data stored in the other of the two mailboxes, and the second processor identifies that the first processor has processed the data stored in the data area when detecting the second information status on the other of the two interrupt pins.

5. The dual processor system as claimed in claim 4 , wherein the first information status is a predetermined low voltage level generated on either of the two interrupt pins, and the second information status is a predetermined high voltage level generated on either of the two interrupt pins.

6. The dual processor system as claimed in claim 3 , wherein the data area includes a plurality of sub data areas, and the first processor stores the data to be processed by the second processor in one of the sub data areas.

7. The dual processor system as claimed in claim 6 , wherein when the second processor is processing the data stored in the one of the sub data areas, the first processor further stores new data to be processed by the second processor in another of the sub data areas; after the first processor identifies that the second processor has processed the data stored in the previous one of the sub data areas, the first processor writes new interrupt data to the configuration area and the one of the two mailboxes, and the DPRAM generates a next first information status on the one of the two interrupt pins; the second processor reads the new interrupt data stored in the configuration area when detecting the next first information status, and processes the new data stored in the another sub data area when successfully reading the new interrupt data stored in the configuration area.

8. A method for using a dual processor system, comprising:

a first processor of the dual processor system storing data to be processed by a second processor of the dual processor system to a data area of a dual-ported random access memory (DPRAM) of the dual processor system, and writing interrupt data to the DPRAM;

the DPRAM generating a first information status;

the second processor reading the interrupt data once when detecting the first information status on the interrupt pin, processing the to be processed data when successfully reading the interrupt data once, and reading the interrupt data twice when completing processing the to be processed data;

the DPRAM generating a second information status when the second processor successfully reading the interrupt data twice, and

the first processor identifying that the second processor has processed the to be processed data when detecting the second information status.

9. The method as claimed in claim 8 , wherein the DPRAM includes a data area, two mailboxes, a configuration area, and two interrupt pins; when the first processor stores data to be processed by the second processor to the data area and writes interrupt data to the configuration area and one of the two mailboxes, the DPRAM generates the first information status on one of the two interrupt pins; the second processor reads the interrupt data stored in the configuration area when detecting the first information status on the one of the two interrupt pins, processes the data stored in the data area when successfully reading the interrupt data stored in the configuration area, and reads the interrupt data stored in the one of the two mailboxes when completing processing the data stored in data area; the DPRAM generates the second information status on the one of the two interrupt pins when the second processor successfully reads the interrupt data stored in the one of the two mailboxes, and the first processor identifies that the second processor has processed the data stored in the data area when detecting the second information status on the one of the two interrupt pins.

10. The method as claimed in claim 9 , further comprising:

the second processor storing data to be processed by the first processor to the data area, and writing interrupt data to the configuration area and the other of the two mailboxes;

the DPRAM generating the first information status on the other of the two interrupt pins;

the first processor reading the interrupt data stored in the configuration area when detecting the first information status on the other of the two interrupt pins, processing the data stored in the data area when successfully reading the interrupt data stored in the configuration area, and reading the interrupt data stored in the other of the two mailboxes when completing processing the data stored in data area;

the DPRAM generating the second information status on the other of the two interrupt pins when the first processor successfully reads the interrupt data stored in the other of the two mailboxes; and

the second processor identifying that the first processor has processed the data stored in the data area when detecting the second information status on the other of the two interrupt pins.

11. The method as claimed in claim 9 , wherein the first information status is a predetermined low voltage level generated on either of the two interrupt pins, and the second information status is a predetermined high voltage level generated on either of the two interrupt pins.

12. The method as claimed in claim 9 , further comprising:

storing the data to be processed by the second processor in one sub data area of the data area;

when the second processor is processing the data stored in the one sub data area of the data area, storing new data to be processed by the second processor in another sub data area of the data area;

after the first processor identifies that the second processor has processed the data stored in the previous one of the sub data areas, writing new interrupt data to the configuration area and the mailbox;

the DPRAM generating a next first information status on the interrupt pin; and

the second processor reading the new interrupt data stored in the configuration area when detecting the next first information status, and processing the new data stored in the another sub data area when successfully reading the new interrupt data stored in the configuration area.