Through-silicon vias for semicondcutor substrate and method of manufacture
A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.
1. A semiconductor component comprising:
a semiconductor substrate having a top surface;
an opening having an interior surface extending from the top surface into the semiconductor substrate, wherein the opening has a top portion and a bottom portion;
a first dielectric liner disposed on the interior surface of the opening, the first dielectric liner having a thickness T 1 on the top portion and a thickness T 2 on the bottom portion, wherein R 1 is a ratio of T 1 to T 2 ;
a second dielectric liner disposed on the first dielectric liner, the second dielectric liner having a thickness T 3 on the top portion and a thickness T 4 on the bottom portion, wherein R 2 is a ratio of T 3 to T 4 , and R 1 is greater than R 2 ;
a third dielectric liner disposed on the second dielectric liner, the third dielectric liner having a thickness T 5 on the top portion and a thickness T 6 on the bottom portion, wherein T 5 is greater than T 6 ;
a metal barrier layer disposed on the third dielectric liner; and
a conductive material disposed on the metal barrier layer and filling the opening.
2. The semiconductor component of claim 1 , wherein the ratio R 1 is about 5 to about 20.
3. The semiconductor component of claim 1 , wherein the ratio R 2 is about 1 to about 5.
4. The semiconductor component of claim 1 , wherein a ratio R 3 of T 5 to T 6 is about 5 to about 20.
5. The semiconductor component of claim 1 , wherein the first dielectric liner has a first etching rate in a HF solution, the second dielectric liner has a second etching rate in the HF solution, and the first etching rate is less than the second etching rate.
6. The semiconductor component of claim 5 , wherein the third dielectric liner has a third etching rate in the HF solution, and the third etching rate is less than the second etching rate.
7. The semiconductor component of claim 1 , wherein the first dielectric liner has a first compressive stress and the third dielectric liner has a second compressive stress, and at least one of the first compressive stress and the second compressive stress is within a range of 100 MPa to 400 Mpa.
8. The semiconductor component of claim 1 , wherein the second dielectric liner has a tensile stress.
9. The semiconductor component of claim 8 , wherein the tensile stress is within a range of 50 MPa to 300 MPa.