Gate depletion drain extended MOS transistor
A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.
1. A semiconductor device comprising at least one gate-depletion drain-extended MOS transistor and at least one other MOS transistor of the same polarity, wherein
the at least one gate-depletion drain-extended MOS transistor and the at least one other MOS transistor each comprise a gate-oxide having an equivalent thickness and a polysilicon gate, and
the polysilicon gate of the at least one gate-depletion drain-extended MOS transistor has a significantly lower doping level than the polysilicon gate of the at least one other MOS transistor; and
the at least one gate-depletion drain-extended MOS transistor comprising a source-side Core extension implant, a source-side Input/Output (I/O) extension implant and a pocket implant, wherein the I/O extension implant is of adequate depth and is of a sufficient doping to overcome the pocket implant so as to prevent bulk leakage, and wherein a doping level of the I/O extension implant is combined with another doping level of the Core extension implant to set the significantly lower doping level of the polysilicon gate of the at least one gate-depletion drain-extended MOS transistor.
2. A semiconductor device according to claim 1 , wherein the duping level of the polysilicon gate of the at least one gate-depletion drain-extended MOS transistor is lower than the doping level of the at least one other MOS transistor by approximately a factor of 5 to 50.
3. A design for a semiconductor device as claimed in claim 1 .
4. A mask set for fabricating a semiconductor device as claimed in claim 1 .