Flash memory device and method of operation
View Patent ↗A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge. Each memory cell further includes circuitry for modulating the erase voltage according to the level of the programming charge on its floating gate.
1. A NAND flash memory device having a memory cell comprising a floating gate, a control gate connected to a wordline and receiving a control voltage therefrom to induce a programming charge on the floating gate, a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge and thereby restore the floating gate to a nominal erased stated thereof, and means for modulating the erase voltage according to the level of the programming charge on the floating gate, the modulating means avoiding deep depletion or over-erasing of the floating gate by only subjecting the memory cell to a pulse at a level of the erase voltage needed to restore the nominal erased state.
2. The NAND flash memory device according to claim 1 , wherein the NAND flash memory device comprises a plurality of memory cells, and each of the memory cells comprises a floating gate, control gate, wordline, bitline, and modulating means as recited in claim 1 .
3. The NAND flash memory device according to claim 1 , wherein the modulating means comprises a bypass circuitry that is activated and de-activated according to the level of the programming charge on the floating gate, and the bypass circuitry decreases the erase voltage when activated.
4. The NAND flash memory device according to claim 3 , wherein the NAND flash memory device comprises a plurality of memory cells, each of the memory cells comprises a floating gate, control gate, wordline, bitline, and modulating means as recited in claim 1 , and each of the bypass circuitries decreases the erase voltage of the memory cell thereof when activated.
5. The NAND flash memory device according to claim 3 , wherein the bypass circuitry is activated by a transistor.
6. The NAND flash memory device according to claim 5 , further comprising a CMOS inverter that inverts the control voltage to turn the transistor “on” if the control voltage is below a threshold level.
7. The NAND flash memory device according to claim 6 , wherein the CMOS inverter inverts the control voltage to turn the transistor “off” if the control voltage is above the threshold level.
8. A method of operating a NAND flash memory device having a memory cell comprising a floating gate, a control gate connected to a wordline to receive a control voltage therefrom and induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge and thereby restore the floating gate to a nominal erased stated thereof, the method comprising decreasing the erase voltage if the control voltage is below a threshold level to avoid over-erasing of the floating gate by only subjecting the memory cell to a pulse at a level of the erase voltage needed to restore the nominal erased state.
9. The method according to claim 8 , wherein the NAND flash memory device comprises a plurality of memory cells, and each of the memory cells comprises a floating gate, control gate, wordline and bitline as recited in claim 8 , and the method comprises individually decreasing the erase voltage applied to any of the memory cells if the control voltage of the memory cell is below the threshold level.
10. The method according to claim 8 , wherein the step of decreasing the erase voltage is performed with a bypass circuitry that is activated and de-activated according to the level of the programming charge on the floating gate, and the bypass circuitry decreases the erase voltage when activated.
11. The method according to claim 10 , wherein the NAND flash memory device comprises a plurality of memory cells, each of the memory cells comprises a floating gate, control gate, wordline, and bitline as recited in claim 8 , and each of the bypass circuitries decreases the erase voltage of the memory cell thereof when activated.
12. The method according to claim 10 , wherein the bypass circuitry is activated by a transistor.
13. The method according to claim 12 , further comprising a CMOS inverter that inverts the control voltage to turn the transistor “on” if the control voltage is below a threshold level.
14. The method according to claim 13 , wherein the CMOS inverter inverts the control voltage to turn the transistor “off” if the control voltage is above the threshold level.
15. A NAND flash memory device having a plurality of memory cells, each of the memory cells comprising a floating gate, a control gate connected to a wordline and adapted to receive a control voltage therefrom to induce a programming charge on the floating gate, a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge, and means for modulating the erase voltage according to the level of the programming charge on the floating gate of each of the memory cells.
16. A NAND flash memory device having a memory cell comprising a floating gate, a control gate connected to a wordline and adapted to receive a control voltage therefrom to induce a programming charge on the floating gate, a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge, and means for modulating the erase voltage according to the level of the programming charge on the floating gate, wherein the modulating means comprises a bypass circuitry that is activated and de-activated according to the level of the programming charge on the floating gate, the bypass circuitry is individually connected to the wordline of the memory cell so that the bypass circuitry is activated depending on the control voltage on the wordline of the memory cell, and the bypass circuitry decreases the erase voltage when activated based on the programming charge on the floating gate.
17. The NAND flash memory device according to claim 16 , wherein the NAND flash memory device comprises a plurality of memory cells, each of the memory cells comprises a floating gate, control gate, wordline, bitline, and modulating means as recited in claim 16 , and each of the bypass circuitries decreases the erase voltage of the memory cell thereof when activated.
18. A method of operating a NAND flash memory device having a plurality of memory cells, each of the memory cells comprising a floating gate, a control gate connected to a wordline to receive a control voltage therefrom and induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge, the method comprising decreasing the erase voltage if the control voltage is below a threshold level to avoid over-erasing of the floating gate of each of the memory cells.
19. A method of operating a NAND flash memory device having a memory cell comprising a floating gate, a control gate connected to a wordline to receive a control voltage therefrom and induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge, the method comprising decreasing the erase voltage if the control voltage is below a threshold level to avoid over-erasing of the floating gate of each of the memory cells, wherein the step of decreasing the erase voltage is performed with a bypass circuitry that is activated and de-activated according to the level of the programming charge on the floating gate, the bypass circuitry is individually connected to the wordline of the memory cell so that the bypass circuitry is activated depending on the control voltage on the wordline of the memory cell, and the bypass circuitry decreases the erase voltage when activated based on the programming charge on the floating gate.
20. The method according to claim 19 , wherein the NAND flash memory device comprises a plurality of memory cells, and each of the memory cells comprises a floating gate, control gate, wordline and bitline as recited in claim 19 , and the method comprises individually decreasing the erase voltage applied to any of the memory cells if the control voltage of the memory cell is below the threshold level.