LDMOS semiconductor device having guardring region disposed at side of well region

1. A Lateral Diffused Metal-Oxide-Semiconductor (LDMOS) device comprising:

a substrate;

a gate region over the substrate;

a source region and a drain region which are formed in the substrate;

an N-well region formed in the substrate and spaced apart from the drain region;

a guardring region connected electrically to the N-well region, wherein the N-well region is located between the drain region and the guardring region; and

a plurality of second P-well regions grounded to the substrate and disposed at both sides of the N-well region and both sides of the guardring region.

2. The LDMOS semiconductor device of claim 1 , wherein the N-well region comprises:

a shallow N-well region doped with an N-type dopant; and

an N+-type region in the shallow N-well region.

3. The LDMOS semiconductor device of claim 1 , further comprising:

a second HV-WELL formed in the substrate and under the gate region, wherein the drain region and the source region are formed in the second HV-WELL.

4. The LDMOS semiconductor device of claim 1 , wherein the guardring region comprises:

a first P-well region in the substrate and connected electrically to the N-well region by a line; and

at least one guardring disposed at least at one side of the first P-well region.

5. The LDMOS semiconductor device of claim 4 , further comprising:

at least one device isolation layer formed between the first P-well region and the at least one guardring.

6. The LDMOS semiconductor device of claim 4 , further comprising:

a first High Voltage (HV)-WELL in the substrate, wherein the guardring region is formed in the first HV-WELL.

7. The LDMOS semiconductor device of claim 6 , further comprising:

a buried layer in the substrate and under the first HV-WELL.

8. The LDMOS semiconductor device of claim 4 , wherein the at least one guardring includes first and second guardrings each disposed at one side of the first P-well region and doped with an N-type dopant.

9. The semiconductor device of claim 8 , further comprising:

a first device isolation layer formed between the first P-well region and the first guardring; and

a second device isolation layer formed between the first P-well region and the second guardring.

10. A LDMOS semiconductor device comprising:

a substrate;

a source region at one side of a gate region;

a drain region at another side of the gate region different than the one side;

at least one N-well region formed in the substrate spaced apart from the drain region;

at least one guardring electrically connected to the at least one N-well region, wherein the at least one N-well region is located between the drain region and the at least one guardring region, wherein the drain region is disposed between the gate region and the gaurdring region; and

a plurality of second P-well regions grounded to the substrate and disposed at both sides of the at least one N-well region and both sides of the at least one quardring region.

11. The LDMOS semiconductor device of claim 10 , wherein the at least one N-well region comprises:

a shallow N-well region doped with an N-type dopant; and

an N+-type region in the shallow N-well region.

12. The LDMOS semiconductor device of claim 10 , wherein the at least one N-well region is connected to the guardring region through at least one line.

13. The semiconductor device of claim 10 , wherein the at least one guardring includes first and second guardrings disposed at both sides of the P-well region.

14. The semiconductor device of claim 13 , further comprising:

a first device isolation layer formed between the P-well region and the first guardring; and

a second device isolation layer formed between the P-well region and the second guardring.

15. A semiconductor device comprising:

a substrate;

a source region and a drain region which are formed in the substrate;

a gate region over the substrate;

at least one N-well region formed in the substrate spaced apart from the source region and the drain region;

a guardring region electrically connected to the at least one N-well region and spaced apart from the at least one N-well region; and

a plurality of second P-well regions grounded to the substrate and disposed at both sides of the at least one N-well region and both sides of the guardring region.