IP Library Granted Patent US 8,603,856
Granted Patent B2
US 8,603,856 · App. 13/090,650 · Granted Dec 10, 2013

Organic transistor and method for manufacturing the same

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Quick Facts
Patent No.
US 8,603,856
App. No.
13/090,650
Granted
Dec 10, 2013
Kind
B2
Abstract

An organic transistor includes an insulating substrate, a gate electrode on the substrate, a gate insulating layer disposed over the substrate and the gate electrode, a source and a drain electrode on the gate insulating layer, a nonpolar macromolecular insulating underlayer disposed on the gate insulating layer at least between the source electrode and the drain electrode, and an organic semiconductor layer disposed on the source electrode and the drain electrode and on the insulating underlayer between the source electrode and the drain electrode.

Claims (14)

1. A method for manufacturing an organic transistor, comprising:

forming a source electrode and a drain electrode on an insulating substrate;

forming an insulating underlayer of nonpolar macromolecular material over the substrate and the source and drain electrodes;

forming an organic semiconductor layer between the source electrode and the drain electrode by applying an organic semiconductor material solution onto the insulating underlayer over the source electrode and the drain electrode and over a region of the insulating underlayer between the source electrode and the drain electrode, the organic semiconductor material solution containing a solvent that dissolves a portion of the insulating underlayer so that the organic semiconductor layer contacts the source electrode and the drain electrode;

forming a gate insulating layer over the insulating underlayer and the organic semiconductor layer; and

forming a gate electrode on the gate insulating layer corresponding to the region between the source electrode and the drain electrode.

2. The method according to claim 1 , further comprising performing surface treatment to impart different surface roughnesses to the substrate and the source and drain electrodes so that the solvent can remove the portions of the insulating underlayer on the source and drain electrodes and allow the portion of the insulating underlayer between the source electrode and the drain electrode to remain, subsequent to the formation of the source and drain electrodes.

3. The method according to claim 1 , further comprising, before the solvent dissolves the portion of the insulating underlayer, the portion of the insulating underlayer is disposed between the organic semiconductor layer and the gate and source electrodes.

4. A method for manufacturing an organic transistor, comprising:

forming a source electrode and a drain electrode over an insulating substrate;

forming an insulating underlayer of nonpolar macromolecular material over the substrate and the source and drain electrodes;

forming an organic semiconductor layer between the source electrode and the drain electrode by applying an organic semiconductor material solution onto the insulating underlayer over the source electrode and the drain electrode and over a region of the insulating underlayer between the source electrode and the drain electrode, the organic semiconductor material solution containing a solvent that dissolves a portion of the insulating underlayer so that the organic semiconductor layer contacts the source electrode and the drain electrode; and

forming an insulating layer over the insulating underlayer and the organic semiconductor layer.

5. The method according to claim 4 , further comprising forming a gate electrode corresponding to the region between the source electrode and the drain electrode, and performing surface treatment to impart different surface roughnesses to the source and drain electrodes so that the solvent can remove the portions of the insulating underlayer on the source and drain electrodes and allow the portion of the insulating underlayer between the source electrode and the drain electrode to remain, subsequent to the forming of the source and drain electrodes.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2018
From: SEIKO EPSON CORPORATION
To: E INK CORPORATION
Reel/Frame 047072/0325 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2011
From: NAKAMURA, KIYOSHI
To: SEIKO EPSON CORPORATION
Reel/Frame 026162/0476 →