Semiconductor devices with sealed, unlined trenches and methods of forming same
A semiconductor device includes unlined and sealed trenches and methods for forming the unlined and sealed trenches. More particularly, a superjunction semiconductor device includes unlined, and sealed trenches. The trench has sidewalls formed of the semiconductor material. The trench is sealed with a sealing material such that the trench is air-tight. First and second regions are separated by the trench. The first region may include a superjunction Schottky diode or MOSFET. In an alternative embodiment, a plurality of regions are separated by a plurality of unlined and sealed trenches.
1. A semiconductor device comprising:
a substrate doped with a dopant of a first conductivity type;
a layer of epitaxial silicon disposed above the substrate, the layer of epitaxial silicon being doped with a dopant of the first conductivity type, the substrate being doped in an amount greater than the epitaxial silicon;
a trench disposed in the layer of epitaxial silicon, the trench having sidewalls comprised of the epitaxial silicon, the trench separating an active region and a termination region of the layer, the active region comprising a superjunction MOSFET structure, the trench being sealed by a sealing material such that the trench is air-tight;
a first metal contact disposed above the active region of the layer of epitaxial silicon and proximate to the trench; and
a second metal contact disposed above the termination region of the layer of epitaxial silicon and proximate to the trench.
2. The semiconductor device of claim 1 , wherein the air-tight trench contains a gas comprising at least one selected from inert gases and air.
3. The semiconductor device of claim 2 , wherein the gas has a pressure lower than about standard atmospheric pressure.
4. The semiconductor device of claim 2 , wherein the gas has a moisture content less than or equal to about 5%.
5. The semiconductor device of claim 1 , wherein the superjunction MOSFET structure includes a trench gate disposed beneath the first metal contact.
6. The semiconductor device of claim 5 , wherein a gate insulating layer is disposed between the trench gate and the first metal contact.
7. The semiconductor device of claim 1 , wherein at least a portion of the sealing material is disposed over the trench and between the first metal contact and the second metal contact.
8. The semiconductor device of claim 1 , wherein the sealing material is disposed entirely within the trench.
9. The semiconductor device of claim 1 , wherein the sealing material is spun-on glass.
10. The semiconductor device of claim 1 , wherein the layer of epitaxial silicon further comprises a plurality of additional trenches in the active region, wherein each additional trench is unlined and has sidewalls comprised of the epitaxial silicon, and wherein each addition trench is sealed with a sealing material such that each additional trench is air-tight.