IP Library Granted Patent US 8,536,673
Granted Patent B2
US 8,536,673 · App. 13/092,578 · Granted Sep 17, 2013

Light receiving circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,536,673
App. No.
13/092,578
Granted
Sep 17, 2013
Kind
B2
Abstract

Provided is a light receiving circuit for detecting a change in amount of light, in which an input circuit at a subsequent stage is compact and inexpensive and current consumption is low. The light receiving circuit includes: a photoelectric conversion element for supplying a current corresponding to an amount of incident light; an N-channel MOS transistor including a drain supplied with the current from the photoelectric conversion element; and a control circuit for controlling a gate voltage of the NMOS transistor via a low pass filter so that a drain voltage of the N-channel MOS transistor becomes a desired voltage. The control circuit outputs a control state output signal, which is a GND terminal voltage when a delay amount of control on the gate voltage of the NMOS transistor performed via the low pass filter is less than a desired delay amount, and is the drain voltage of the NMOS transistor when the delay amount of control on the gate voltage of the NMOS transistor performed via the low pass filter is the desired delay amount or more. The light receiving circuit outputs the control state output signal as an output signal.

Claims (9)

1. A light receiving circuit, comprising:

an output terminal;

a photoelectric conversion element configured to supply a current corresponding to an amount of incident light;

an NMOS transistor comprising a drain connected with, and configured to receive the current from, the photoelectric conversion element; and

a control circuit comprising a delay circuit; an input terminal that is at the same potential as the drain of the NMOS transistor; a control terminal connected to a gate of the NMOS transistor; and a control state output terminal connected to the output terminal,

wherein the control circuit is configured to output via the control state output terminal a control state output signal corresponding to a delay of the delay circuit when a drain voltage of the NMOS transistor is changed, and

wherein the light receiving circuit outputs, via the output terminal, the control state output signal as a detection signal of a change in the amount of the incident light.

2. The light receiving circuit according to claim 1 , wherein the delay circuit comprises a low pass filter.

3. The light receiving circuit according to claim 1 , wherein the photoelectric conversion element comprises a PN diode, including a P terminal connected to the drain of the NMOS transistor and an N terminal connected to a VDD terminal.

Assignments (5)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
CHANGE OF NAME Recorded Mar 12, 2018
From: SII SEMICONDUCTOR CORPORATION
To: ABLIC INC.
Reel/Frame 045567/0927 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 037783 FRAME: 0166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 23, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION
Reel/Frame 037903/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2016
From: SEIKO INSTRUMENTS INC
To: SII SEMICONDUCTOR CORPORATION .
Reel/Frame 037783/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2011
From: UTSUNOMIYA, FUMIYASU; YAMASAKI, TARO; FUJII, ISAMU
To: SEIKO INSTRUMENTS INC.
Reel/Frame 026170/0504 →