Biphase mark code decoder and method of operation
View Patent ↗Biphase mark codes (BMC) are used in digital communications. Most BMC formats use preambles for rate determination and synchronization. A decoder compares the intervals of continuous high or continuous low voltages in a BMC stream to predetermined minimum and maximum values of half cell, full cell and one-and-a-half cell intervals for all supported sampling rates. If a pattern matching a preamble is found, the sampling rate is locked in and the decoder is synchronized to the BMC stream. Once locked, the decoder uses the predetermined minimum and maximum values at the locked rate to generate half cell, full cell and one-and-a-half cell indicators for a decoding state machine which decodes data in the BMC stream or decodes expected preambles.
1. A decoder comprising:
an interval width comparator comprising a synchronization module and an interval width discriminator module; and
a decoder state machine;
wherein the synchronization module is configured to compare a plurality of past interval widths with a plurality of maximum and minimum data values for a 0.5 T interval, a 1.0 T interval and a 1.5 T interval for a plurality of sampling rates and to determine whether a match with a preamble pattern comprising some or all of the group consisting of 0.5 T interval, 1.0 OT interval and 1.5 T interval has been detected, and to select a sampling rate when a match is detected.
2. The decoder of claim 1 wherein the interval width discriminator module is configured to receive an interval width, to compare the interval width with a plurality of maximum and minimum values for a 0.5 T interval, a 1.0 T interval and a 1.5 T interval for the sampling rate selected by the synchronization module, and to provide an 0.5 T indicator, 1.0 T indicator or 1.5 T indicator to the decoder state machine.
3. The decoder of claim 1 further comprising a lookup table storing the plurality of maximum and minimum data values.
4. The BMC decoder of claim 1 further comprising an interval counter operable to count oversampling clock cycles between transitions between a low voltage and a high voltage.
5. The BMC decoder of claim 1 further comprising a high pulse counter operable to count consecutive oversampling clock cycles while the input to the BMC decoder is high and a low pulse counter operable to count consecutive oversampling clock cycles while the input to BMC decoder is low.
6. The BMC decoder of claim 1 wherein the input receives a Sony/Phillips Digital Interface Format (SPDIF).
7. The BMC decoder of claim 1 wherein the input receives an Audio Engineering Society 3 (AES3) format.
8. A method of decoding a data stream comprising:
synchronizing a counter to a preamble in the data stream;
determining a sampling rate associated with the data stream;
decoding data from the data stream using the sampling rate;
wherein synchronizing the counter to the preamble in the data stream comprises:
(a) receiving an interval width;
(b) selecting a rate from a plurality of supported sampling rates;
(c) retrieving a maximum and a minimum value for a 0.5 T interval, a 1.0 T interval, a 1.5 T interval at the selected rate;
(d) determining whether the interval width and a plurality of recent intervals matches a preamble pattern associated with the preamble, said determining comprises comparing the interval width and the plurality of recent intervals to the maximum value and minimum value retrieved;
(e) if the interval width and plurality of recent intervals matches the preamble pattern then locking the rate;
(f) otherwise repeating (b)-(e) until all rates in the plurality of supported sampling rates have been selected or until the rate is locked; and
(g) repeating (a)-(f) until the rate is locked.
9. The method of claim 8 , wherein decoding data from the data stream using the sampling rate comprises:
receiving an interval width;
comparing the interval width with a maximum value and a minimum value corresponding to the 0.5 T interval;
providing a 0.5 T indicator to a decoding state machine if the interval width lies between the maximum value and the minimum value corresponding to the 0.5 T interval;
comparing the interval width with a maximum value and a minimum value corresponding to the 1.0 T interval;
providing a 1.0 T indicator to a decoding state machine if the interval width lies between the maximum value and the minimum value corresponding to the 1.0 T interval;
comparing the interval width with a maximum value and a minimum value corresponding to the 1.5 T interval; and
providing a 1.5 T indicator to a decoding state machine if the interval width lies between the maximum value and the minimum value corresponding to the 1.5 T interval.
10. The method of claim 8 wherein retrieving a maximum and a minimum value for an 0.5 T interval, a 1.0 T interval, a 1.5 T interval at the selected rate comprises looking up the maximum and minimum value in a lookup table.
11. The method of claim 8 further comprising counting oversampling clock cycles between transitions between a low voltage and a high voltage in the data stream.
12. The method of claim 8 further comprising:
counting consecutive oversampling clock cycles while the data stream is high; and
counting consecutive oversampling clock cycles while the data stream is low.
13. The method of claim 8 wherein the data stream is an SPDIF stream.
14. The method of claim 8 wherein the data stream is an AES3 stream.
15. A decoder comprising:
an interval width comparator further comprising:
a synchronization module configured to compare a plurality of past interval widths of a data stream with a plurality of maximum and minimum data values for a plurality of predetermined intervals and at a plurality of sampling rates, to determine whether a match with a preamble pattern has been detected, and to generate a synchronization signal; and
an interval state discriminator module configured to decode the data stream if the synchronization signal has been generated; and
a decoder state machine for transitioning between a synchronization mode and a decoder mode as a function of the data stream.
16. The decoder of claim 15 further comprising a lookup table storing the plurality of maximum and minimum data values.
17. The decoder of claim 15 further comprising an interval counter configured to count clock cycles between transitions between a low voltage and a high voltage.
18. The decoder of claim 15 further comprising a high pulse counter configured to count consecutive clock cycles while the input to the decoder is high.
19. The decoder of claim 18 further comprising a low pulse counter configured to count consecutive clock cycles while the input to decoder is low.