IP Library Granted Patent US 8,471,493
Granted Patent B2
US 8,471,493 · App. 13/093,592 · Granted Jun 25, 2013

Combination LED driver

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,471,493
App. No.
13/093,592
Granted
Jun 25, 2013
Kind
B2
Abstract

A driver circuit for a Light Emitting Diode (LED) is disclosed. The driver circuit is capable of supporting a constant LED current circuit configuration as well as an external resistor-controlled LED current circuit configuration. By integrating both configurations into a single driver circuit, the either circuit configuration can be selected without requiring a different driver circuit.

Claims (25)

1. A circuit arrangement for controlling current flowing through an LED, the circuit arrangement comprising:

a transistor comprising first, second, and third terminals, the first terminal of the transistor being configured to be electrically connected to the LED; and

a transistor input circuit configured to receive a control signal and being connected to the second terminal of the transistor, the transistor input circuit comprising first circuitry configured to control current flowing through an LED via the transistor with or without a resistor connected in series with the LED, second circuitry configured to control current flowing through an LED via the transistor only with a resistor connected in series with the LED, and at least one switch configured to control whether the first circuitry or second circuitry carries the control signal to the second terminal of the transistor.

2. The circuit arrangement of claim 1 , wherein the first terminal comprises a transistor drain, wherein the second terminal comprises a transistor gate, and wherein the third terminal comprises a transistor source.

3. The circuit arrangement of claim 2 , wherein the transistor source is connected to ground.

4. The circuit arrangement of claim 1 , wherein the transistor comprises an NMOS.

5. The circuit arrangement of claim 1 , wherein the first circuitry comprises current control circuitry, wherein the second circuitry comprises one or more inverters, and wherein the transistor comprises a plurality of transistors.

6. The circuit arrangement of claim 5 , wherein the at least one switch comprises one or more transmission gates.

7. The circuit arrangement of claim 1 , wherein the first terminal is connected to an IC input.

8. An Integrated Circuit comprising the circuit arrangement of claim 1 .

9. An Integrated Circuit comprising a transistor input circuit enabling the Integrated Circuit to drive a first LED circuit arrangement when the transistor input circuit is in a first operational state as well as drive a second LED circuit arrangement when the transistor input circuit is in a second operational state, wherein the first LED circuit arrangement comprises an LED without an external resistance connected in series therewith, and wherein the second LED circuit arrangement comprises an LED with an external resistance connected in series therewith.

10. The Integrated Circuit of claim 9 , wherein the external resistance connected in series with the LED in the second LED circuit arrangement controls the amount of current which flows through the LED.

11. The Integrated Circuit of claim 9 , wherein a common control input is used by the transistor input circuit in both the first and second operational states.

12. The Integrated Circuit of claim 11 , further comprising one or more switches which switch whether the transistor input circuit is in the first or second operational state.

13. The Integrated Circuit of claim 12 , wherein the one or more switches comprise one or more transmission gates.

14. The Integrated Circuit of claim 13 , wherein the Integrated Circuit also drives the second LED circuit arrangement in the second operational state.

15. The Integrated Circuit of claim 12 , wherein the transistor comprises a gate, drain, and source terminal.

16. The Integrated Circuit of claim 15 , further comprising an input pin that is connected to the transistor drain.

17. A transistor input circuit connected to a transistor, the transistor input circuit configured to control current flowing through a diode via the transistor, the transistor input circuit comprising:

first circuitry configured to control current flowing through the diode with or without a resistor connected in series with the diode;

second circuitry configured to control current flowing through the diode only with a resistor connected in series with the diode; and

a switch configured to control whether the first circuitry or second circuitry is electrically connected to the transistor.

18. The circuit of claim 17 , wherein the first and second circuitry are connected in parallel.

19. The circuit of claim 17 , wherein the first circuitry comprises current control circuitry, wherein the second circuitry comprises one or more inverters, and wherein the switch comprises a transmission gate.

20. The circuit of claim 17 , wherein the diode comprises an LED.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded May 1, 2013
From: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030331/0533 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2011
From: YEM, POH WENG; CHANG, KENG YEAM; TEH, LEE LING
To: AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD.
Reel/Frame 026177/0310 →