WRITE SCHEME IN PHASE CHANGE MEMORY
A method for writing a phase change memory includes receiving an input data corresponding to a plurality of memory cells, while reading a previous data from the plurality of memory cells and comparing the input data with the previous data. Upon determining that the input data is different from the previous data for one or more of the plurality of memory cells, and upon determining that a current value of a write counter is less than a maximum value, one or more of the plurality of memory cells is programmed with the input data and the current value of the writer counter is incremented.
1 . A method for writing a phase change memory comprising:
receiving an input data corresponding to a plurality of memory cells, while reading a previous data from the plurality of memory cells and comparing the input data with the previous data; and
upon determining that the input data is different from the previous data for one or more of the plurality of memory cells, and upon determining that a current value of a write counter is less than a maximum value, programming the one or more of the plurality of memory cells with the input data and incrementing the current value of the write counter.
2 . The method of claim 1 wherein receiving an input data further comprises receiving a burst of the input data, the burst including a plurality of data-words.
3 . The method of claim 2 wherein the burst of the input data is received with a single data rate (SDR), wherein each of the plurality of data-words is clocked on one clock edge.
4 . The method of claim 2 wherein the burst of the input data is received with a double data rate (DDR), wherein each of the plurality of data-words is clocked on one of a rising and a falling clock edge.
5 . The method of claim 1 wherein the input data is stored in a register, the previous data is stored in a sense amplifier, and comparing the input data with the previous data occurs in the sense amplifier with the comparison results communicated to a write driver.
6 . The method of claim 1 wherein the input data is stored in a register, the previous data is stored in a sense amplifier, and comparing the input data with the previous data occurs in the register with the comparison results communicated to a write driver.
7 . The method of claim 1 wherein the current value of the write counter is initially set to zero.
8 . The method of claim 1 wherein a fail flag is set when the current value is equal to the maximum value.
9 . An apparatus for writing a phase change memory comprising:
a sense amplifier including a bias transistor and a differential voltage amplifier, the bias transistor in communication with a positive input of a differential voltage amplifier, one of a plurality of memory cells in communication with the positive input of the differential voltage amplifier, a sense voltage at the positive input of the differential voltage amplifier being in proportion to a bias resistance of the bias transistor and a memory cell resistance of the one of the plurality of memory cells, a reference voltage in communication with a negative input of the differential voltage amplifier, the reference voltage being between the sense voltage obtained at the positive input of the differential voltage amplifier for the one of the plurality of memory cells in a SET state and the one of the plurality of memory cells in a RESET state;
a register retaining the state of a plurality of bits in a data-word;
a write driver having a write current branch, a reset current branch and a set current branch, the reset current branch enabled by a RESET state and disabled by a data-mask state, the set current branch enabled by a SET state and disabled by the data-mask state, the write current branch mirroring a current of one of the reset current branch and the set current branch; and
an equivalence circuit setting the data-mask state corresponding to a bit in the data-word having the SET state when a corresponding sensed bit in the plurality of memory cells has the SET state, and setting the data-mask state corresponding to a bit in the data-word having the RESET state when a corresponding sensed bit in the plurality of memory cells has the RESET state.
10 . The apparatus of claim 9 wherein the equivalence circuit is an exclusive-NOR gate, the corresponding sensed bit in communication with one input of the exclusive-NOR gate, and the bit in the data-word in communication with another input of the exclusive-NOR gate.
11 . The apparatus of claim 9 wherein the plurality of memory cells includes a phase change memory.
12 . The apparatus of claim 9 wherein a first duration for the register to receive a burst of data-words substantially overlaps with a second duration for the sense amplifier to sense one of the plurality of memory cells and for the equivalence circuit to set the data-mask state.
13 . The apparatus of claim 12 wherein the burst of the data-words includes eight data words.
14 . A phase change memory system comprising:
a memory array including a plurality of memory cells, each of the plurality of memory cells located at one of a plurality of rows and at one of a plurality of columns;
a plurality of local column selectors, each local column selector being in communication with a plurality of columns;
a global column selector in communication with the plurality of local column selectors;
a sense amplifier in communication with the global column selector, the sense amplifier including a bias transistor and a differential voltage amplifier, the bias transistor in communication with a positive input of a differential voltage amplifier, one of a plurality of memory cells in communication with the positive input of the differential voltage amplifier, a sense voltage at the positive input of the differential voltage amplifier being in proportion to a bias resistance of the bias transistor and a memory cell resistance of the one of the plurality of memory cells, a reference voltage in communication with a negative input of the differential voltage amplifier, the reference voltage being between the sense voltage obtained at the positive input of the differential voltage amplifier for the one of the plurality of memory cells in a set state and the one of the plurality of memory cells in a reset state;
a register retaining the state of a plurality of bits in a data-word;
a write driver in communication with the global column selector, the write driver having a write current branch, a reset current branch and a set current branch, the reset current branch enabled by a reset state and disabled by a data-mask state, the set current branch enabled by a set state and disabled by the data-mask state, the write current branch mirroring a current of one of the reset current branch and the set current branch; and
an equivalence circuit setting the data-mask state corresponding to a bit in the data-word having the set state when a corresponding sensed bit in the plurality of memory cells has the set state, and setting the data-mask state corresponding to a bit in the data-word having the reset state when a corresponding sensed bit in the plurality of memory cells has the reset state.
15 . The system of claim 14 wherein the equivalence circuit is an exclusive-NOR gate, the corresponding sensed bit in communication with one input of the exclusive-NOR gate, and the bit in the data word in communication with another input of the exclusive-NOR gate.
16 . The system of claim 14 wherein the plurality of memory cells includes a phase change memory.
17 . The system of claim 14 wherein a first duration for the register to receive a burst of data-words substantially overlaps with a second duration for the sense amplifier to sense one of the plurality of memory cells and for the equivalence circuit to set the data-mask state.
18 . The system of claim 17 wherein the burst of the data-words includes eight data words.