System and method for handling system failure
View Patent ↗A system and a method for handling a system failure are disclosed. The method is adapted for an information handling system having a basic input and output system and a micro-controller. The method includes the following steps: sending, via the micro-controller, a signal; checking, via the micro-controller, whether an acknowledgement is received from the basic input and output system responsive to the signal; and scanning, via the micro-controller, a type of a system failure in response to the acknowledgement being not received.
1. A system for handling a system failure, comprising:
a basic input and output system; and
a micro-controller;
wherein said micro-controller sends a signal, and in response to failing to receive an acknowledgement responsive to said signal from said basic input and output system, said micro-controller scans a type of a system failure.
2. The system of claim 1 , further comprising:
a peripheral device; and
a status register corresponding in position to said peripheral device;
wherein said micro-controller scans said status register to confirm a failure occurring to said peripheral device, and said micro-controller stores said failure of said peripheral device.
3. The system of claim 1 , further comprising:
a memory; and
a status register corresponding in position to said memory;
wherein said micro-controller scans said status register to confirm a failure occurring to said memory, and said micro-controller stores said failure of said memory.
4. The system of claim 1 , further comprising:
a processor; and
a status register corresponding in position to said peripheral device;
wherein said micro-controller scans said status register to confirm a failure occurring to said processor, and said micro-controller stores said failure of said processor.
5. The system of claim 1 , wherein, in response to a result of said scanning indicates said type of said system failure, said micro-controller marks said type and restarts said system.
6. The system of claim 1 , wherein, in response to a result of said scanning indicates said type of said system failure, said micro-controller marks said type, and said basic input and output system resets a system configuration file.
7. The system of claim 1 , further comprising a chipset coupled between said basic input and output system and said micro-controller, wherein said signal triggers a system management interrupt (SMI) of said chipset, and a system management interrupt (SMI) handling procedure of said basic input and output system serves said system management interrupt (SMI) and generates said acknowledgement.