Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit
View Patent ↗In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
1. A semiconductor integrated circuit device comprising:
a plurality of input/output circuits arranged along by a chip end side of a chip on which the input/output circuits are formed;
wherein each input/output circuit includes:
a logic circuit;
a level conversion circuit coupled to the logic circuit;
a pre-buffer coupled to the level conversion circuit;
an NMOS output buffer and a PMOS output buffer coupled to an I/O pad and arranged to be driven by the pre-buffer;
a first electrostatic breakdown protective circuit coupled between the pre-buffer and the PMOS output buffer;
a second electrostatic breakdown protective circuit coupled between the pre-buffer and the NMOS output buffer;
a third electrostatic breakdown protective circuit coupled between the logic circuit and the level conversion circuit;
the PMOS output buffer is placed nearer than the first electrostatic breakdown protective circuit to the I/O pad; and
the NMOS output buffer is placed nearer than the second electrostatic breakdown protective circuit to the I/O pad.
2. A semiconductor integrated circuit device according to claim 1 , further comprising:
power supply wirings extending between corresponding circuit blocks of adjacent input/output circuits in a direction perpendicular to the direction of extension of the input/output circuits, said logic circuit, said level conversion circuit, said pre-buffer, said NMOS output buffer, said PMOS output buffer, and said first and second electrostatic breakdown protective circuits each comprising one of said circuit blocks; and
an inter-power supply protective device including protective couplings between different power supplies coupled to said power supply wirings and between a power supply and a ground coupled to said power supply wirings.
3. A semiconductor integrated circuit device according to claim 2 ,
wherein said inter-power supply protective device includes diode connections formed between said different power supplies and between said power supply and ground, said diode connections being embodied by at least one of all N-type diffusion layer formed in a P-type well formed in a substrate, a P-type diffusion layer formed in an N-type well formed in an N-type element formation region formed in said substrate, an N-type diffusion layer formed in a P-type well formed in said N-type element formation region, and a P-type diffusion layer formed in an N-type well formed in said substrate.