Method of manufacturing a semiconductor device having an active region and dummy patterns
View Patent ↗There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP 1 of relatively wider area and the second dummy pattern DP 2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP 1 occupy a relatively wide region among the dummy region FA.
1. A method of manufacturing a semiconductor device comprising steps of:
(a) forming a first insulating film over a semiconductor substrate;
(b) after the step (a), forming a first conductive film over the first insulating film;
(c) after the step (b), forming a mask layer over the first conductive film;
(d) after the step (c), patterning the first insulating film, the first conductive film and the mask layer;
(e) after the step (d), forming grooves in the semiconductor substrate by using the patterned mask layer, thereby an active region, a plurality of first dummy regions and a plurality of second dummy regions are formed in the semiconductor substrate;
(f) after the step (e), forming element isolation regions by embedding second insulating films into the grooves;
(g) after the step (f), removing the patterned mask layer; and
(h) after the step (g), forming a second conductive film over the first conductive film,
wherein, in the active region, the first and second conductive films constitute a gate electrode of a MISFET,
wherein, in the active region, the first insulating film constitutes a gate insulating film of the MISFET,
wherein a planar size of each of the first dummy regions is larger than a planar size of each of the second dummy regions, and
wherein each of the first dummy regions is arranged with same pitch,
wherein each of the second dummy regions is arranged with same pitch, and
wherein the second dummy regions are arranged next to the first dummy regions, and are arranged between the active region and the first dummy regions.
2. The method of manufacturing a semiconductor device according to claim 1 ,
wherein, at the step (f), the second insulating films are polished by CMP method.
3. The method of manufacturing a semiconductor device according to claim 1 ,
wherein the pitch of the first dummy regions is larger than the pitch of the second dummy regions.
4. The method of manufacturing a semiconductor device according to claim 1 ,
wherein the first conductive film is made of a poly silicon film.
5. The method of manufacturing a semiconductor device according to claim 4 ,
wherein the second conductive film is made of a poly silicon film.
6. The method of manufacturing semiconductor device according to claim 1 ,
wherein the mask layer is made of a silicon nitride film.
7. A method of manufacturing a semiconductor device comprising steps of:
(a) forming a first insulating film over a semiconductor substrate;
(b) after the step (a), forming a first conductive film over the first insulating film;
(c) after the step (b), patterning the first insulating film and the first conductive film;
(d) after the step (c), forming grooves in the semiconductor substrate between the patterned first insulating film and the patterned first conductive film, thereby an active region, a plurality of first dummy regions and a plurality of second dummy regions are formed in the semiconductor substrate;
(e) after the step (d), forming element isolation regions by embedding second insulating films into the grooves;
(f) after the step (e), forming a second conductive film over the first conductive film,
wherein, in the active region, the first and second conductive films constitute a gate electrode of a MISFET,
wherein, in the active region, the first insulating film constitutes a gate insulating film of the MISFET,
wherein a planar size of each of the first dummy regions is larger than a planar size of each of the second dummy regions, and
wherein each of the first dummy regions is arranged with same pitch,
wherein each of the second dummy regions is arranged with same pitch, and
wherein the second dummy regions are arranged next to the first regions, and are arranged between the active region and the first dummy regions.
8. The method of manufacturing a semiconductor device according to claim 7 ,
wherein, at the step (e), the second insulating films are polished by CMP method.
9. The method of manufacturing a semiconductor device according to claim 7 ,
wherein the pitch of the first dummy regions is larger than the pitch of the second dummy regions.
10. The method of manufacturing a semiconductor device according to claim 7 ,
wherein the first conductive film is made of a poly silicon film.
11. The method of manufacturing a semiconductor device according to claim 10 ,
wherein the second conductive film is made of a poly silicon film.
12. The method of manufacturing a semiconductor device according to claim 7 ,
wherein the mask layer is made of a silicon nitride film.