System for managing memory
View Patent ↗Systems and methods that manage memory are provided. In one embodiment, a system for communications may include, for example, a memory management system that may handle a first application employing a virtual address based tagged offset and a second application employing a zero based tagged offset with a common set of memory algorithms.
1. A system for handling memory accesses by a user space application and a non-user space application, comprising:
a host operatively coupled to one or more host buffers;
a network interface card (NIC) interface operatively coupled to the one or more host buffers; and
a memory region that spans some of the one or more host buffers, wherein one or both of the host and the NIC interface advertise the memory region using both a virtual address based tagged offset and a zero based tagged offset depending upon whether the memory region being accessed by the user space application or the non-user space application, wherein the advertising includes advertising the memory region using a first base offset (FBO), and
wherein a lower layer protocol application or a device inserts information related to the FBO in a message advertising the memory region.
2. The system according to claim 1 , wherein both the virtual address based tagged offset and the zero based tagged offset are stored in a common format in a memory management system.
3. The system according to claim 1 , wherein a common set of memory management algorithms is used based on whether an application uses the virtual address based tagged offset or the zero based tagged offset.
4. The system according to claim 1 , wherein an upper layer protocol application or an upper layer protocol device is unaware of the use of the FBO.
5. The system according to claim 1 , wherein the lower layer protocol application inserts the information related to the FBO in the message advertising the memory region.
6. The system according to claim 1 , wherein the device inserts information related to the FBO in the message advertising the memory region.
7. The system according to claim 6 , wherein the device includes a remote direct memory access (RDMA) interface.
8. The system according to claim 6 , wherein the device includes a network interface card.
9. The system according to claim 1 , wherein the lower layer protocol application uses RDMA.
10. A system for handling memory accesses by a user space application and a non-user space application, comprising:
a host operatively coupled to a host memory region;
a network interface card (NIC) interface operatively coupled to the host memory region; and
the memory region that is accessible by the user space application and the non-user space application using a common set of memory management algorithms, wherein one or both of the host and the NIC interface advertise the memory region using both a virtual address based tagged offset and a zero based tagged offset, wherein the advertising includes advertising the memory region using a first base offset (FBO), and
wherein a lower layer protocol application or a device inserts information related to the FBO in a message advertising the memory region.
11. The system according to claim 10 , wherein both the virtual address based tagged offset and the zero based tagged offset are stored in a common format in a memory management system.
12. The system according to claim 10 , wherein an upper layer protocol application or an upper layer protocol device is unaware of the use of the FBO.
13. The system according to claim 10 , wherein the lower layer protocol application inserts the information related to the FBO in the message advertising the memory region.
14. The system according to claim 10 , wherein the device inserts the information related to the FBO in the message advertising the memory region, and wherein the device include one or more of the following: a remote direct memory access (RDMA) interface and a network interface card.
15. A system for handling memory accesses by a user space application and a non-user space application, comprising:
a host operatively coupled to a host memory region;
a network interface card (NIC) interface operatively coupled to the host memory region; and
the memory region, wherein one or both of the host and the NIC interface advertise the memory region using both a virtual address based tagged offset and a zero based tagged offset, wherein the advertising includes advertising the memory region using a first base offset (FBO), wherein both the virtual address based tagged offset and the zero based tagged offset are stored in a common format in a memory management system, and
wherein a lower layer protocol application or a device inserts information related to the FBO in a message advertising the memory region.
16. The system according to claim 15 , wherein the device inserts the information related to the FBO in the message advertising the memory region, and wherein the device include one or more of the following: a remote direct memory access (RDMA) interface and a network interface card.