Thin film transistor liquid crystal display array substrate and manufacturing method thereof

1. A method of manufacturing a TFT LCD array substrate, comprising the steps of:

1) depositing in sequence a gate metal layer, a gate insulating dielectric layer and a semiconductor layer on a substrate, then performing masking and etching by a gray tone mask to form a gate line, a gate electrode connected with the gate line, a gate insulating layer, and a semiconductor layer for a thin film transistor, wherein the semiconductor layer and the gate insulating layer have a width less than that of the gate electrode so that each side of the gate electrode is exposed by the semiconductor layer and the gate insulating layer;

2) depositing an isolating dielectric layer on the resultant substrate after step 1, then performing masking and etching processes with respect to the isolating dielectric layer to form via holes in the isolating dielectric layer on both sides of the semiconductor layer;

3) forming an ohmic contact layer in the via holes obtained in the step 2; and

4) depositing a pixel electrode layer and a source/drain electrode metal layer on the resultant substrate after the step 3, then performing masking and etching with a gray tone mask to form a transparent pixel electrode, a source electrode, a drain electrode and a data line, wherein the drain electrode is integrated with the data line.

2. The method according to claim 1 , wherein, during the masking with a gray tone mask in the step 1, a partially transparent portion of the gray tone mask corresponds to the gate line and gate electrode to be formed, a opaque portion of the gray tone mask to the semiconductor layer of the TFT to be formed, and a transparent portion of the gray tone mask to remaining portion of the substrate.

3. The method according to claim 1 , wherein, during the masking with a gray tone mask in the step 4, a partially transparent portion of the gray tone mask corresponds to the transparent pixel electrode to be formed, a opaque portion of the gray tone mask to the source electrode, the drain electrode and the data line to be formed, and a transparent portion of the gray tone mask to remaining portion of the substrate.

4. The method according to claim 1 , wherein, the step 3 of fabricating an ohmic contact layer is to introduce PH 3 and H 2 into a plasma enhanced chemical vapor deposition chamber, induce a surface reaction between the PH 3 and H 2 in plasma state and amorphous silicon in the via holes, and form a μc-Si layer in the via holes under properly controlled reaction conditions.

5. The method according to claim 1 , wherein, the step 3 of fabricating an ohmic contact layer is to use a high temperature photoresist during masking for the via holes, then not perform the photoresist lift-off process, directly deposit a μc-Si layer by plasma enhanced chemical vapor deposition, and strip off the photoresist and the μc-Si layer thereon by photoresist lift-off process, thereby forming a μc-Si layer in the via holes.

6. The method according to claim 1 , wherein, the step 3 of fabricating an ohmic contact layer is to use a high temperature photoresist during the masking for the via holes, then not perform the photoresist lift-off process, deposit a layer of n + a-Si by chemical vapor deposition and then a very thin metal layer of Mo, Cr, W, or alloys thereof, and strip off the photoresist and the n + a-Si layer and the metal layer of Mo, Cr, W, or alloys thereof on the photoresist by photoresist lift-off process, thereby forming a n + a-Si layer and a metal layer of Mo, Cr, W, or alloys thereof in the via holes.

7. The method according to claim 1 , wherein, the step 4 of depositing the pixel electrode layer and the source/drain electrode metal layer is performed in a same or different equipment sequentially.