IP Library Granted Patent US 8,539,140
Granted Patent B2
US 8,539,140 · App. 13/096,731 · Granted Sep 17, 2013

Storage device including flash memory and capable of predicting storage device performance based on performance parameters

Inventor: Akihisa Fujimoto (Fussa, JP)
Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,539,140
App. No.
13/096,731
Granted
Sep 17, 2013
Kind
B2
Abstract

A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.

Claims (21)

1. A host apparatus comprising an application which has a plurality of write modes with different bit rates and which transfers data to a storage device which stores performance parameters relevant to performance of the storage device, wherein

an operation mode of a bus between the host apparatus and the storage device is selected among operation modes,

the performance parameters include information for computing performance to write data into a semiconductor memory in the storage device,

the minimum bit rate of the storage device to write data into the semiconductor memory in the storage device via the bus with the selected operation mode is determined by information for computing performance, and

the host apparatus makes a change to an application bit rate lower relative to a bit rate of the storage device determined based on the information for computing performance.

2. The apparatus according to claim 1 , wherein the apparatus further reads the performance parameters from the storage device, and executes a calculation using the performance parameters.

3. The apparatus according to claim 2 , wherein the apparatus further manages a memory area of the semiconductor memory in the storage device by management unit areas each comprising write unit areas, and

classifies the management unit areas into a suitable management unit area capable of storing data with a requested performance and an unsuitable management unit area incapable of storing data with the requested performance in accordance with a condition of the management unit areas using the performance parameters.

4. The apparatus according to claim 3 , wherein the apparatus uses the suitable management unit area for real-time write.

5. The apparatus according to claim 1 , wherein the apparatus calculates available recording time for which data is written with the requested performance using an average bit rate with which the apparatus transfers write data to the storage device and how many the suitable management unit areas remain unused.

6. The apparatus according to claim 1 , wherein the apparatus determines that a performance class is not defined in the storage device when the performance class information of the storage device is “0”.

7. The apparatus according to claim 1 , wherein the apparatus writes data to the storage device with a second bit rate lower than a first bit rate when performance of the storage device does not satisfy the first bit rate required by the host apparatus.

8. The apparatus according to claim 1 , wherein the apparatus stores data requested to be written in a buffer of the host apparatus while data write to the storage device is impossible.

9. The apparatus according to claim 1 , further comprising:

a cover; and

a display portion provided on the cover and displaying a performance class set to the host apparatus.

10. The apparatus according to claim 1 , wherein the host apparatus changes the application bit rate mode to be lower than the bit rate of the storage device based on the information for computing performance.

11. A method for selecting a combination of an operation mode and an associated bit rate in a host apparatus, comprising:

selecting, by an application executing in the host apparatus, an operation mode from a plurality of operation modes of a bus between the host apparatus and a storage device to which data is transferred, the storage device storing performance parameters including information for computing performance on writing data to a semiconductor memory in the storage device, the operation mode being associated with a plurality of bit rates;

determining the minimum bit rate for the storage device for writing data to the semiconductor memory in the storage device, via the bus, with the selected operation mode, based on the information for computing performance; and

changing, by the host apparatus, to an application bit rate lower than a bit rate of the storage device determined based on the information for computing performance.

Assignments (4)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043328/0388 →
Priority Claims (2)
JP 2004-204028 · Jul 12, 2004 · national
JP 2004-342275 · Nov 26, 2004 · national
Continuity (3)
Division 11557120 · Nov 7, 2006
Continuation PCTJP2005013104 · Jul 8, 2005
Related Publication 20110202712A1 · Aug 18, 2011