Thin film transistor substrate and flat panel display apparatus
View Patent ↗A thin film transistor substrate including a plurality of thin film transistors, and a flat panel display apparatus. Each of the plurality of thin film transistors includes an active layer comprising a first channel region having a first plurality of protrusion lines arranged therein and a second channel region and having a second plurality of protrusion lines arranged therein, a source electrode and a drain electrode electrically connected to the active layer and a gate electrode insulated from the active layer, wherein the first and second plurality of protrusion lines extend in a first direction, wherein a edges of the first channel region that extend in the first direction and are offset sideways by a distance in a second direction that is orthogonal to the first direction from corresponding edges of the second channel region that extend in the first direction.
1. A thin film transistor substrate comprising a plurality of thin film transistors, wherein each of the plurality of thin film transistors comprises:
an active layer comprising a first channel region having a first plurality of protrusion lines arranged therein and a second channel region and having a second plurality of protrusion lines arranged therein;
a source electrode and a drain electrode electrically connected to the active layer; and
a gate electrode insulated from the active layer, wherein the first and second plurality of protrusion lines extend in a first direction, wherein a edges of the first channel region that extend in the first direction and are offset sideways by a distance in a second direction that is orthogonal to the first direction from corresponding edges of the second channel region that extend in the first direction.
2. The thin film transistor substrate of claim 1 , wherein the first plurality is unequal to the second plurality.
3. The thin film transistor substrate of claim 1 , wherein the first plurality differs from the second plurality by 1.
4. The thin film transistor substrate of claim 1 , wherein the first channel region and the second channel region extend in the second direction.
5. The thin film transistor substrate of claim 1 , wherein a length of the first channel region extending in the second direction is equal to a length of the second channel region extending in the second direction.
6. The thin film transistor substrate of claim 1 , wherein neighboring ones of the first plurality of protrusion lines and neighboring ones of the second plurality of protrusion lines are spaced apart from each other at regular intervals.
7. The thin film transistor substrate of claim 1 , wherein the active layer further comprises:
an intermediate region arranged between the first channel region and the second channel region; and
a source region and a drain region arranged on sides of the first channel region and the second channel region opposite from the intermediate region.
8. The thin film transistor substrate of claim 7 , wherein both edges of the intermediate region extending from the first channel region to the second channel region form an oblique angle with the first direction.
9. The thin film transistor substrate of claim 1 , wherein the gate electrode comprises:
a first gate electrode overlapping the first channel region; and
a second gate electrode overlapping the second channel region.
10. A flat panel display apparatus comprising a display device and a plurality of thin film transistors, each of the plurality of thin film transistors comprises:
an active layer comprising a first channel region having a first plurality of protrusion lines arranged therein and a second channel region and having a second plurality of protrusion lines arranged therein;
a source electrode and a drain electrode electrically connected to the active layer; and
a gate electrode insulated from the active layer, wherein the first and second plurality of protrusion lines extend in a first direction, wherein edges of the first channel region that extend in the first direction and are offset sideways by a distance in a second direction that is orthogonal to the first direction from corresponding edges of the second channel region that extend in the first direction.
11. The flat panel display apparatus of claim 10 , wherein the first plurality is unequal to the second plurality.
12. The flat panel display apparatus of claim 10 , wherein the first plurality differs from the second plurality by 1.
13. The flat panel display apparatus of claim 10 , wherein the first channel region and the second channel region extend in the second direction.
14. The flat panel display apparatus of claim 10 , wherein a length of the first channel region extending in the second direction is equal to a length of the second channel region extending in the second direction.
15. The flat panel display apparatus of claim 10 , wherein neighboring ones of the first plurality of protrusion lines and neighboring ones of the second plurality of protrusion lines are spaced apart from each other at regular intervals.
16. The flat panel display apparatus of claim 10 , wherein the active layer further comprises:
an intermediate region arranged between the first channel region and the second channel region; and
a source region and a drain region arranged on sides of the first channel region and the second channel region that are opposite from the intermediate region.
17. The flat panel display apparatus of claim 16 , wherein both edges of the intermediate region extending from the first channel region to the second channel region form an oblique angle with the first direction.
18. The flat panel display apparatus of claim 10 , wherein the gate electrode comprises:
a first gate electrode overlapping the first channel region; and
a second gate electrode overlapping the second channel region.
19. The flat panel display apparatus of claim 10 , wherein the display device is selected from a group consisting of an organic light-emitting diode display device and a liquid crystal display device.
20. The flat panel display apparatus of claim 10 , wherein the display device is electrically connected to at least one of the plurality of thin film transistors.