Thin film transistor array panel and manufacturing method thereof
View Patent ↗A thin film transistor array panel is provided that includes: a gate electrode that is disposed on an insulating substrate; a gate insulating layer that is disposed on the gate electrode; an oxide semiconductor that is disposed on the gate insulating layer; a blocking layer that is disposed on the oxide semiconductor; a source electrode and a drain electrode that are disposed on the blocking layer; a passivation layer that is disposed on the source electrode and drain electrode; and a pixel electrode that is disposed on the passivation layer. The blocking layer includes a first portion that is covered by the source electrode and drain electrode and a second portion that is not covered by the source electrode and drain electrode, and the first portion and the second portion include different materials.
1. A thin film transistor array panel, comprising:
a gate electrode disposed on a substrate;
a gate insulating layer disposed on the gate electrode;
an oxide semiconductor disposed on the gate insulating layer;
a blocking layer disposed on the oxide semiconductor;
a source electrode and a drain electrode disposed on the blocking layer;
a passivation layer disposed on the source electrode and drain electrode; and
a pixel electrode disposed on the passivation layer, wherein,
the blocking layer comprises a first portion that is covered by the source electrode and the drain electrode, and a second portion that is disposed on a channel region of the oxide semiconductor,
the first portion of the blocking layer pattern comprises a silicide or amorphous silicon,
the second portion of the blocking layer pattern comprises silicon oxide (SiO x ), and
the silicon oxide (SiO x ) content of the second portion is greater than the silicon oxide (SiO x ) content of the first portion.
2. The thin film transistor array panel of claim 1 , wherein the second portion of the blocking layer is electrically insulating.
3. The thin film transistor array panel of claim 1 , wherein the oxide semiconductor layer comprises gallium indium zinc oxide (GIZO).
4. The thin film transistor array panel of claim 1 , wherein the oxide semiconductor layer comprises:
a lower layer that comprises gallium indium zinc oxide (GIZO); and
an upper layer that comprises GIZO, the upper layer having a lower indium content than the lower layer.
5. The thin film transistor array panel of claim 1 , wherein the source electrode and drain electrode each comprise a lower layer and an upper layer.
6. The thin film transistor array panel of claim 5 , wherein:
the lower layer comprises titanium (Ti) and
the upper layer comprises copper (Cu).
7. The thin film transistor array panel of claim 1 , wherein
the oxide semiconductor layer comprises gallium indium zinc oxide (GIZO), ZnSnO (ZTO), or indium zinc oxide (IZO).
8. The thin film transistor array panel of claim 7 , wherein the oxide semiconductor layer comprises:
a lower layer that comprises GIZO; and
an upper layer that comprises GIZO, the upper layer having a lower indium content than the lower layer.
9. A method for manufacturing a thin film transistor array panel, comprising:
forming a gate electrode on a substrate;
forming a gate insulating layer on the gate electrode;
forming an oxide semiconductor layer on the gate insulating layer;
forming a blocking layer on the oxide semiconductor layer;
forming a metal layer on the blocking layer;
forming a first photosensitive film pattern on the metal layer;
etching the metal layer, the blocking layer, and the oxide semiconductor layer, using the first photosensitive film pattern as a mask, to form a metal layer pattern, a blocking layer pattern, and an oxide semiconductor layer pattern;
performing an etch-back process on the first photosensitive film pattern, so as to form a second photosensitive film pattern that comprises an opening disposed above a channel region of the oxide semiconductor layer pattern;
etching the metal layer through the opening, to form a source electrode and a drain electrode on the blocking layer;
oxidizing a portion of the blocking layer pattern that is disposed above the channel region of the oxide semiconductor layer pattern, such that the oxide semiconductor layer pattern has a first portion that is not oxidized and a second portion that is oxidized;
forming a passivation layer on the source electrode and the drain electrode; and
forming a pixel electrode on the passivation layer, wherein,
the first portion of the blocking layer pattern comprises a silicide or amorphous silicon,
the second portion of the blocking layer pattern comprises silicon oxide (SiO x ), and
the silicon oxide (SiO x ) content of the second portion is greater than the silicon oxide (SiO x ) content of the first portion.
10. The method of claim 9 , wherein the first photosensitive film pattern comprises:
a first portion having a first thickness; and
a second portion having a second thickness that is less than the first thickness.
11. The method of claim 10 , wherein the second portion of the first photosensitive film pattern is disposed over the channel region.
12. The method of claim 10 , wherein the thickness of the second photosensitive film pattern is less than the thickness of the first portion of the first photosensitive film pattern.
13. The method of claim 9 , wherein the oxide semiconductor layer pattern comprises gallium indium zinc oxide (GIZO), ZnSnO (ZTO), or indium zinc oxide (IZO).
14. The method of claim 9 , wherein the oxide semiconductor layer pattern comprises:
a lower layer that comprises gallium indium zinc oxide (GIZO); and
an upper layer that comprises GIZO, the upper layer having a lower indium content than the lower layer.
15. The method of claim 9 , wherein the source electrode and drain electrode each comprise:
a lower layer that comprises titanium (Ti); and
an upper layer that comprises copper (Cu).