Rate matching and de-rate matching on digital signal processors
View Patent ↗Provided are systems and methods for rate matching and de-rate matching on digital signal processors. For example, there is a system for rate matching and de-rate matching, where the system includes a memory configured to contain a plurality of blocks of data, and a digital signal processor configured to pre-compute permutation parameters common to the plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters. The digital signal processor is configured to process each block in the plurality of blocks by computing a block signature from pre-computed puncturing thresholds, matching the block signature to one of a set of pre-computed zone signatures, deriving a zone index corresponding to the one matched pre-computed zone signature, and applying pre-computed permutation and puncturing transformations corresponding to the zone index to the block.
1. An apparatus, comprising: a digital signal processor configured to: pre-compute permutation parameters common to a plurality of blocks, wherein the plurality of blocks are subject to a set of given puncturing parameters; and for each block in the plurality of blocks: compute a block signature from pre-computed puncturing thresholds; match the block signature to one of a set of pre-computed zone signatures; derive a zone index corresponding to the one matched pre-computed zone signature; apply pre-computed permutation and puncturing transformations corresponding to the zone index to the block.
2. The apparatus of claim 1 , wherein the digital signal processor is further configured to: load the block into a vector register after deriving the zone index.
3. The apparatus of claim 2 , wherein the digital signal processor is further configured to perform at least one of: apply the pre-computed permutation and puncturing transformations to the packed block in the vector register; unpack the transformed block in the vector register; or write the unpacked transformed block in the vector register to the memory.
4. The apparatus of claim 1 , wherein the pre-computed permutation and puncturing transformations are applied to the block.
5. The apparatus of claim 1 , wherein the transformed block is written to the vector register.