Microcomputer outputting failure detection result
View Patent ↗When a CPU executes a failure detection program, the CPU causes a program counter expected value register to store an expected value of an address which is stored in a program counter after a detection time passes from the start of execution of the failure detection program, and causes a detection time counter to start counting of the detection time. When the detection time counter finishes counting of the detection time, the first comparator outputs as a failure detection result a result of comparison between the address stored in the program counter and the expected value stored in the program counter expected value register.
1. A microcomputer, comprising:
a CPU including a program counter which updates and stores an address of an instruction of a program to be executed next when an instruction of the program is executed, the CPU configured to execute instructions of the program of which addresses stored in the program counter in order;
a program counter expected value register which stores an expected value of an address to be stored in the program counter;
a first comparator which compares the address stored in the program counter with the expected value stored in the program counter expected value register; and
a detection time counter which counts a detection time,
wherein when the CPU executes a failure detection program, the CPU causes the program counter expected value register to store the expected value of the address which is stored in the program counter after the detection time passes from the start of execution of the failure detection program, and causes the detection time counter to start counting of the detection time, and
wherein when the detection time counter finishes counting of the detection time, the first comparator outputs as a failure detection result a result of comparison between the address stored in the program counter and the expected value stored in the program counter expected value register.
2. The microcomputer according to claim 1 ,
wherein when the first comparator outputs a comparison result indicating inconsistency, the CPU determines that a failure of the CPU is detected and performs failure countermeasure processing.
3. The microcomputer according to claim 1 , further comprising:
a detection time register which stores a detection time; and
a second comparator which compares the detection time stored in the detection time register with a count value of the detection time counter,
wherein when instructed by the CPU to start counting, the detection time counter starts up counting of a count value,
wherein when the CPU executes the failure detection program, the CPU causes the detection time register to store the detection time, and
wherein when the second comparator outputs a comparison result indicating a match between the detection time stored in the detection time register and the count value of the detection time counter, the first comparator outputs as a failure detection result a result of comparison between the address stored in the program counter and the expected value stored in the program counter expected value register.
4. The microcomputer according to claim 3 ,
wherein when the CPU executes the failure detection program, the CPU causes the detection time counter to start up counting from 0 (zero).
5. The microcomputer according to claim 1 ,
wherein when instructed by the CPU to start counting, the detection time counter starts down counting of a count value.
6. The microcomputer according to claim 5 ,
wherein when the CPU executes the failure detection program, the CPU causes the detection time counter to start down counting from the detection time, and
wherein when the count value of the detection time counter becomes 0 (zero), the first comparator outputs as a failure detection result a result of comparison between the address stored in the program counter and the expected value stored in the program counter expected value register.