IP Library Granted Patent US 8,489,855
Granted Patent B2
US 8,489,855 · App. 13/103,270 · Granted Jul 16, 2013

NAND flash-based solid state drive and method of operation

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,489,855
App. No.
13/103,270
Granted
Jul 16, 2013
Kind
B2
Abstract

A solid state drive that uses over-provisioning of NAND flash memory blocks as part of housekeeping functionality, including deduplication and coalescence of data for efficient usage of NAND flash memory devices and maintaining sufficient numbers of erased blocks to promote write performance.

Claims (31)

1. A solid state drive adapted for use with a host system, the solid state drive comprising:

a controller; and

at least one NAND flash-based non-volatile memory device comprising pages that are organized into memory blocks, the memory blocks being minimum-erasable units of the memory device, the pages being sequentially programmable and readable such that some of the memory blocks are partially written blocks, the memory blocks being partitioned into at least first and second pools that constitute two virtual address spaces of the memory device, the first pool being a user-accessible pool to which the controller virtually assigns a plurality of the memory blocks as user-accessible memory blocks, and the second pool being an over-provisioning pool to which the controller virtually assigns a plurality of the memory blocks as over-provisioned memory blocks;

wherein the solid state drive is adapted to operate such that each of the memory blocks can be transitioned between the user-accessible pool and the over-provisioning pool, data are written to pages of the memory blocks virtually assigned to either the user-accessible pool or the over-provisioning pool, pages from a first partially written block are copied into a second partially written block without accessing the host system, and the first partially written block is erased to constitute an erased block after all pages of the first partially written block have been copied to the second partially written block and without a TRIM or erase command from the host system.

2. The solid state drive of claim 1 , wherein the pages copied from the first partially written block to the second partially written block are read into a buffer on the controller before being written back to the second partially written block.

3. The solid state drive of claim 2 , wherein the memory blocks are virtually assigned to the user-accessible pool or the over-provisioning pool on the basis of a wear-leveling algorithm performed by the controller.

4. The solid state drive of claim 1 , wherein the pages copied from the first partially written block to the second partially written block are read into a cache not integrated onto the controller before being written back to the second partially written block.

5. The solid state drive of claim 4 , wherein the memory blocks are virtually assigned to the user-accessible pool or the over-provisioning pool on the basis of a wear-leveling algorithm performed by the controller.

6. The solid state drive of claim 1 , further comprising a translation lookaside buffer that is updated when the pages are copied from the first partially written block to the second partially written block.

7. The solid state drive of claim 1 , wherein the solid state drive is adapted to operate such that the erased block is assigned to the over-provisioning pool to maintain a capacity of the over-provisioning pool.

8. The solid state drive of claim 1 , further comprising a content-addressable memory that keeps track of virtual mapping of physical addresses of the memory devices.

9. The solid state drive of claim 1 , wherein the solid state drive is installed and operating in the host system.

10. The solid state drive of claim 9 , wherein the host system is a processing apparatus chosen from the group consisting of personal computers and workstations.

11. A solid state drive adapted for use with a host system, the solid state drive comprising:

a controller; and

at least one NAND flash-based non-volatile memory device comprising pages that are organized into memory blocks, the memory blocks being minimum-erasable units of the memory device, the pages being sequentially programmable and readable such that some of the memory blocks are partially written blocks, the memory blocks being partitioned into at least first and second pools that constitute two virtual address spaces of the memory device, the first pool being a user-accessible pool to which the controller virtually assigns a plurality of the memory blocks as user-accessible memory blocks, and the second pool being an over-provisioning pool to which the controller virtually assigns a plurality of the memory blocks as over-provisioned memory blocks;

wherein the solid state drive is adapted to operate such that each of the memory blocks can be transitioned between the user-accessible pool and the over-provisioning pool, data are written to pages of the memory blocks virtually assigned to either the user-accessible pool or the over-provisioning pool, pages from a first partially written block in the over-provisioning pool are copied into a second partially written block in the user-accessible pool using a buffer on the controller without accessing the host system, and the first partially written block is erased to constitute an erased block after all pages of the first partially written block have been copied to the second partially written block and without a TRIM or erase command from the host system.

12. The solid state drive of claim 11 , further comprising a content-addressable memory that keeps track of virtual mapping of physical addresses of the memory devices.

13. A method of operating a solid state drive within a host system, the solid state drive comprising a controller and at least one NAND flash-based non-volatile memory device comprising pages that are organized into memory blocks, the memory blocks being minimum-erasable units of the memory device, the pages being sequentially programmable and readable such that some of the memory blocks are partially written blocks, the method comprising:

partitioning the memory blocks into at least first and second pools that constitute two virtual address spaces of the memory device, the first pool being a user-accessible pool and the second pool being an over-provisioning pool;

operating the controller to virtually assign to the user-accessible pool a plurality of the memory blocks as user-accessible memory blocks, virtually assign to the over-provisioning pool a plurality of the memory blocks as over-provisioned memory blocks, and transition the memory blocks between the user-accessible pool and the over-provisioning pool;

writing data to pages of the memory blocks virtually assigned to either the user-accessible pool or the over-provisioning pool;

copying pages from a first partially written block into a second partially written block without accessing the host system; and

erasing the first partially written block to constitute an erased block after all pages of the first partially written block have been copied to the second partially written block, wherein the erasing step is performed without a TRIM or erase command from the host system.

14. The method of claim 13 , wherein the pages copied from the first partially written block to the second partially written block are read into a buffer on the controller before being written back to the second partially written block.

15. The method of claim 13 , wherein the pages copied from the first partially written block to the second partially written block are read into a cache not integrated onto the controller before being written back to the second partially written block.

16. The method of claim 13 , wherein the memory blocks are partitioned to the first and second pools on the basis of a wear-leveling algorithm performed by the controller.

17. The method of claim 13 , further comprising updating a translation lookaside buffer when the pages are copied from the first partially written block to the second partially written block.

18. The method of claim 13 , further comprising assigning the erased block to the over-provisioning pool to maintain a capacity of the over-provisioning pool.

19. The method of claim 13 , further comprising tracking virtual mapping of physical addresses of the memory devices with a content-addressable memory.

20. The method of claim 13 , wherein the host system is a processing apparatus chosen from the group consisting of personal computers and workstations.

Assignments (15)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2017
From: TOSHIBA CORPORATION
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043620/0430 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2016
From: OCZ STORAGE SOLUTIONS, INC.
To: TOSHIBA CORPORATION
Reel/Frame 038434/0371 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 031611/0168) Recorded Apr 8, 2014
From: COLLATERAL AGENTS, LLC
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0455 →
RELEASE OF SECURITY INTEREST BY BANKRUPTCY COURT ORDER (RELEASES REEL/FRAME 030092/0739) Recorded Apr 8, 2014
From: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 032640/0284 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE AND ATTACH A CORRECTED ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 032365 FRAME 0920. ASSIGNOR(S) HEREBY CONFIRMS THE THE CORRECT EXECUTION DATE IS JANUARY 21, 2014. Recorded Mar 18, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032461/0486 →
CHANGE OF NAME Recorded Feb 27, 2014
From: TAEC ACQUISITION CORP.
To: OCZ STORAGE SOLUTIONS, INC.
Reel/Frame 032365/0945 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2014
From: OCZ TECHNOLOGY GROUP, INC.
To: TAEC ACQUISITION CORP.
Reel/Frame 032365/0920 →
SECURITY AGREEMENT Recorded Nov 11, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: COLLATERAL AGENTS, LLC
Reel/Frame 031611/0168 →
SECURITY AGREEMENT Recorded Mar 27, 2013
From: OCZ TECHNOLOGY GROUP, INC.
To: HERCULES TECHNOLOGY GROWTH CAPITAL, INC.
Reel/Frame 030092/0739 →
RELEASE OF SECURITY INTEREST Recorded Mar 26, 2013
From: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 030088/0443 →
SECURITY AGREEMENT Recorded May 14, 2012
From: OCZ TECHNOLOGY GROUP, INC.
To: WELLS FARGO CAPITAL FINANCE, LLC, AS AGENT
Reel/Frame 028440/0866 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2011
From: SCHUETTE, FRANZ MICHAEL
To: OCZ TECHNOLOGY GROUP, INC.
Reel/Frame 026320/0800 →