IP Library Granted Patent US 8,552,540
Granted Patent B2
US 8,552,540 · App. 13/104,620 · Granted Oct 8, 2013

Wafer level package with thermal pad for higher power dissipation

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Quick Facts
Patent No.
US 8,552,540
App. No.
13/104,620
Granted
Oct 8, 2013
Kind
B2
Abstract

Wafer level packaging (WLP) packages semiconductor dies onto a wafer structure. After the wafer level package is complete, individual packages are obtained by singulating the wafer level package. The resulting package has a small form factor suitable for miniaturization. Unfortunately conventional WLP have poor heat dissipation. An interposer with a thermal pad can be attached to the semiconductor die to facilitate improved heat dissipation. In one embodiment, the interposer can also provide a wafer substrate for the wafer level package. Furthermore, the interposer can be constructed using well established and inexpensive processes. The thermal pad attached to the interposer can be coupled to the ground plane of a system where heat drawn from the semiconductor die can be dissipated.

Claims (15)

1. A method of packaging a semiconductor into a package comprising:

attaching a semiconductor die to a wafer;

applying a first passivation layer;

forming openings in the first passivation layer including an opening for a thermal pad;

depositing metal into the openings in the first passivation layer to partially form the thermal pad;

applying a second passivation layer;

forming openings in the second passivation layer including an opening for the thermal pad and one or more openings for electrodes;

depositing metal into the opening in the second passivation layer for the thermal pad to complete the thermal pad;

depositing metal into the one or more openings for electrodes in the second passivation layers to complete the electrodes; and

singulating the package into individual packages.

2. The method of claim 1 , wherein the first passivation layer and the second passivation comprise a dielectric.

3. The method of claim 1 further comprising forming one or more metal bumps on the thermal pad.

4. The method of claim 1 further comprising forming one or more metal bumps on the electrodes.

5. The method of claim 1 wherein depositing metal into the openings in the first passivation layer to partially form the thermal pad further comprises depositing metal traces for a distribution layer.

6. The method of claim 1 wherein depositing metal into the openings in the first passivation layer to partially form the thermal pad further comprises forming one or more metal pillars.

Assignments (8)
SECURITY INTEREST Recorded Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2017
From: CONEXANT SYSTEMS, LLC
To: SYNAPTICS INCORPORATED
Reel/Frame 043786/0267 →
CHANGE OF NAME Recorded Jun 26, 2017
From: CONEXANT SYSTEMS, INC.
To: CONEXANT SYSTEMS, LLC
Reel/Frame 042986/0613 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2016
From: LAKESTAR SEMI INC.
To: CONEXANT SYSTEMS, INC.
Reel/Frame 038803/0693 →
CHANGE OF NAME Recorded May 20, 2016
From: CONEXANT SYSTEMS, INC.
To: LAKESTAR SEMI INC.
Reel/Frame 038777/0885 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
To: CONEXANT SYSTEMS, INC.; CONEXANT, INC.; CONEXANT SYSTEMS WORLDWIDE, INC.; BROOKTREE BROADBAND HOLDING, INC.
Reel/Frame 038631/0452 →
SECURITY AGREEMENT Recorded Jul 11, 2011
From: CONEXANT SYSTEMS, INC.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 026571/0825 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2011
From: WARREN, ROBERT W.; ROSSI, NIC
To: CONEXANT SYSTEMS, INC.
Reel/Frame 026258/0234 →