Method and circuit to discharge bit lines after an erase pulse

1. A method comprising:

erasing multiple cells in a memory device,

discharging a semiconductor well of a first conduction type and a source line associated with the multiple cells through a first discharge path using a first discharger circuit,

discharging a bit line associated with the multiple cells through a second discharge path using a second discharger circuit, and

determining whether a voltage of the second discharge path is lower than a predetermined voltage using a sensing circuit.

2. The method of claim 1 , comprising:

ending the discharge steps when it is determined that the voltage of the second discharge path is lower than the predetermined voltage.

3. The method of claim 1 , comprising:

shorting the second discharge path with the first discharge path when it is determined that the voltage of the second discharge path is lower than the predetermined voltage, and

after shorting the second discharge path with the first discharge path, determining whether the voltage of the second discharge path is lower than the predetermined voltage using the sensing circuit.

4. The method of claim 3 , comprising:

ending the discharge steps when it is determined that the voltage of the second discharge path is lower than the predetermined voltage after shorting the second discharge path with the first discharge path.

5. The method of claim 3 , comprising:

continuing the discharge steps until it is determined that the voltage of the second discharge path is lower than the predetermined voltage after shorting the second discharge path with the first discharge path.

6. The method of claim 1 , wherein the sensing circuit is a first sensing circuit, the method comprising:

determining whether a voltage of the first discharge path is lower than a predetermined voltage using a second sensing circuit, and

ending the discharge steps when it is determined that the voltage of the first discharge path and the voltage of the second discharge path are each lower than the predetermined voltage.

7. The method of claim 1 , comprising:

determining whether a voltage of the first discharge path is lower than a predetermined voltage using a sensing circuit,

shorting the first discharge path with the second discharge path,

after shorting the first discharge path with the second discharge path, determining whether the voltage of the first discharge path is lower than the predetermined voltage using the sensing circuit, and

ending the discharge steps when it is determined that the voltage of the first discharge path is lower than the predetermined voltage after shorting the first discharge path with the second discharge path.

8. The method of claim 1 , wherein the discharging steps are performed simultaneously.

9. The method of claim 1 , wherein the well of the first conduction type comprises a p-well bulk region and wherein the bit lines are also discharged through capacitive coupling with the p-well bulk region.

10. A method comprising:

driving, to an intermediate voltage, a gate of at least one transistor connecting multiple bit-lines to a common node that is left floating during application of an erase pulse to a bulk region common to the multiple memory cells;

enabling a bit-line discharge path by activating a discharger circuit connected to the common node in response to removal of the erase pulse; and

allowing bit-line discharge to continue, independently of whether the bulk region stops discharging, until the common node voltage is below a desired value.

11. The method of claim 10 , comprising:

sensing when at least one of the common node voltage and the bulk region voltage is below a desired voltage level.

12. The method of claim 10 , wherein the bit-lines are fully dischargeable to substantially ground potential.

13. The method of claim 10 , wherein the at least one transistor comprises a high voltage NMOS transistor.

14. The method of claim 10 , wherein the bulk region comprises a p-well.

15. A method comprising:

performing an erase operation on multiple cells in a memory device,

the performing comprising:

applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up,

discharging the bit lines by coupling the bit lines to a discharging line through a DC path,

discharging a bulk region in which the multiple cells are formed by coupling the bulk region to the discharging line, and

electrically connecting the bulk region and the bit lines to each other when a potential on the bit lines reaches a predetermined level.

16. The method of claim 15 , comprising:

stopping the discharging the bit lines when the potential on the bit lines reaches the predetermined level and resuming the discharging the bit lines in case of the potential of the bit lines becomes larger than the predetermined level due to electrically connecting the bit lines and the bulk region to each other.

17. The method of claim 15 , comprising:

discharging a bulk region in which the multiple cells and a contact region for the bit lines are formed by forwardly biasing a p-n junction between the bulk region and the contact region in response to the discharging the bit lines.

18. The method of claim 15 , wherein the discharging the bit lines and the discharging the bulk region are carried out simultaneously with each other.

19. The method of claim 15 , wherein the discharging the bit lines is carried out after the discharging the bulk region.

20. A device comprising:

a non-volatile memory array including a plurality of cells;

an erase circuit erasing data from the cells;

a first discharger circuit discharging a bit line associated with the cells;

a first sensing circuit supplying a first level of a first signal while a voltage level of the bit line is on or above a first voltage and supplying a second level of the first signal while the voltage level of the bit line is below the first voltage; and

a control circuit deactivating the first discharger circuit in response to receiving the second level of the first signal supplied from the first sensing circuit, to finish the discharging of the bit line which has been charged up by the erasing of the erase circuit.

21. The device of claim 20 , comprising:

a second discharger circuit discharging a semiconductor well associated with the cells, and

wherein the control circuit deactivates the second discharger circuit in response to receiving the second level of the first signal supplied from the first sense circuit, to finish the discharging of the semiconductor well which has been charged up by the erasing of the erase circuit.

22. The device of claim 20 , comprising:

a second discharger circuit discharging a semiconductor well associated with the cells, and

a second sense circuit supplying a first level of a second signal while a voltage level of the semiconductor well is on or above a second voltage and supplying a second level of the second signal while the voltage level of the semiconductor well is below the second voltage; and

wherein the control circuit deactivates the second discharger circuit in response to receiving the second level of the second signal supplied from the second sensing circuit, to finish the discharging of the semiconductor well which has been charged up by the erasing of the erase circuit.

23. The device of claim 20 , comprising:

a switch circuit coupled between a first path connected to the bit line and a second path connected to the semiconductor well, the first and second paths being electrically connected each other when the switch circuit is activated and electrically disconnected each other when the switch circuit is deactivated; and

wherein the control circuit activates the switch circuit in response to receiving the second level of the second signal supplied from the second sensing circuit.

24. The device of claim 20 , wherein the first voltage is power supply of the device.