System for detecting a reset condition in an electronic circuit
View Patent ↗A system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.
1. A system for detecting a physical disturbance affecting a volatile storage of a computing device, said system comprising:
a plurality of circuit elements for outputting a string of data values, said plurality of circuit elements outputting an arbitrary pattern of data values upon power up of said computing device; at least one output of said plurality of circuit elements operable to be affected by said physical disturbance;
a comparator, including an input, said input for receiving said string of data values and determining whether said pattern of said string of data values changes, wherein said comparator detects said change in said pattern and generates a reset signal to reset said computing device.
2. The system of claim 1 wherein said comparator comprises a single logic gate for receiving said set of signals at said input and producing said reset signal.
3. The system of claim 1 wherein said plurality of circuit elements comprises flip flops.
4. The system of claim 1 wherein said system is within an integrated circuit and said reset signal provides a system-wide reset of said integrated circuit.
5. The system of claim 1 wherein said plurality of circuit elements comprises volatile memory, and wherein said predetermined pattern is stored in non-volatile memory accessible by said comparator.
6. The system of claim 1 wherein said disturbance is any one of a power glitch, electromagnetic radiation or voltage drop capable of upsetting volatile storage.
7. The system of claim 1 wherein said plurality of circuit elements are sensitive when a voltage level drops below a level required to maintain state information in said plurality of circuit elements.