Method and circuit for encoding and transmitting numerical values from an analog-to-digital conversion process

1. An analog-to-digital converter system, comprising:

an analog-to-digital converter circuit configured to provide sequentially a plurality of codes during a conversion period;

an encoder interface circuit configured to receive the plurality of codes and to derive a redundant digital representation;

the encoder interface circuit being further configured to transmit a portion of the redundant digital representation during the conversion period; and

wherein the encoder interface circuit is configured to narrow a numerical uncertainty range of the redundant digital representation in response to the analog-to-digital converter circuit providing a code in the plurality of codes.

2. The analog-to-digital converter system of claim 1 wherein the encoder interface circuit is configured to derive the redundant digital representation using a numerical successive-approximation algorithm.

3. The analog-to-digital converter system of claim 1 , wherein the encoder interface circuit comprises a digital state machine configured to be clocked in response to the analog-to-digital converter circuit providing a code in the plurality of codes.

4. The analog-to-digital converter system of claim 1 , wherein the redundant digital representation comprises:

a first code representing a first numerical value;

a second code representing a second numerical value;

where the first and second codes are distinct segments of a composite code designating a numerical value.

5. The analog-to-digital converter system of claim 4 wherein the first numerical value and the second numerical value are combined using addition to calculate the numerical value designated by the composite code.

6. The analog-to-digital converter system of claim 4 wherein the first and second codes are binary-weighted representations of the first and second numerical values.

7. The analog-to-digital converter system of claim 1 wherein the encoder interface circuit is configured to implement a limiting operation.

8. The analog-to-digital converter system of claim 1 , wherein the encoder interface circuit is configured to transmit a group of at least two bits of the redundant digital representation during a period of a clock signal.

9. The analog-to-digital converter system of claim 8 , wherein the encoder interface circuit is configured to transmit a first bit at a rising edge of the clock signal and a second bit at a falling edge of the clock signal.

10. The analog-to-digital converter system of claim 1 , wherein the encoder interface circuit is configured to transmit the redundant digital representation during a transmission period, where at least a half of the transmission period overlaps the conversion period.

11. The analog-to-digital converter system of claim 1 wherein the analog-to-digital converter circuit is configured to operate with a successive-approximation algorithm.

12. An analog-to-digital converter system, comprising:

an analog-to-digital converter circuit configured to provide sequentially a plurality of codes during a conversion period;

an encoder interface circuit configured to receive the plurality of codes and to derive a redundant digital representation;

the encoder interface circuit being further configured to transmit a portion of the redundant digital representation during the conversion period; and

wherein the analog-to-digital converter circuit is configured to operate with a digital overlap algorithm.

13. The analog-to-digital converter system of claim 1 , wherein the analog-to-digital converter circuit is configured to operate with a digital correction algorithm.

14. The analog-to-digital converter system of claim 1 , wherein the plurality of codes consists of a first number of codes provided sequentially by the analog-to-digital converter circuit, and wherein a code of the redundant digital representation comprises a second number of bits, where the second number is greater than the first number.

15. A method for encoding and transmitting a first numerical value obtained from a sequential analog-to-digital conversion process implemented by an analog-to-digital converter circuit, comprising the steps of:

receiving a first set of codes that are defined for a first number systems; the first set of codes confining the first numerical value to be enclosed by a first numerical uncertainty range;

providing a second number system, different from the first number system, using codes to designate numerical values;

assigning a digital state to a portion of a code defined for the second number system to define a second numerical uncertainty range enclosing the first numerical uncertainty range; and

transmitting a signal representing the assigned digital state of the portion of the code defined for the second number system before the analog-to-digital conversion process completes.

16. The method of claim 15 further comprising the step of:

implementing a numerical successive-approximation algorithm to define the second numerical uncertainty range enclosing the first numerical uncertainty range.

17. The method of claim 15 further comprising the steps of:

using a first segment of a code defined for the second number system to define a first-segment numerical value;

using a second segment of the code defined for the second number system to define a second-segment numerical value;

combining the first-segment numerical value and the second-segment numerical value using addition.

18. The method of claim 17 wherein the first segment and the second segment of the code defined for the second number system are interchangeable.

19. The method of claim 15 further comprising the step of:

implementing a digital correction algorithm in the analog-to-digital conversion process.