Method for manufacturing thin film transistor array panel
View Patent ↗A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SF 6 or SF 6 /He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.
1. A method for manufacturing a thin film transistor array panel, the method comprising:
forming a gate line comprising a gate electrode on a substrate;
forming a gate insulating layer on the gate line;
forming a first amorphous silicon layer, a second amorphous silicon layer, a first metal layer, and a second metal layer on the gate insulating layer;
forming a photoresist pattern having a first portion and a second portion on the second metal layer, the thickness of the second portion being greater than the thickness of the first portion;
forming a second metal pattern and a first metal pattern by respectively etching the second metal layer and the first metal layer using the photoresist pattern as a mask;
processing the first metal pattern with SF 6 or a gas mixture comprising SF 6 and He;
forming an amorphous silicon pattern and a semiconductor pattern by respectively etching the second amorphous silicon layer and the first amorphous silicon layer using the photoresist pattern as a mask;
removing the first portion of the photoresist pattern;
forming an upper layer of a data wire by wet etching the second metal pattern using the second portion as a mask;
forming a lower layer of the data wire and an ohmic contact, respectively, by etching the first metal pattern and the amorphous silicon pattern using the second portion as a mask;
forming a passivation layer comprising a contact hole on the upper layer after removing the second portion; and
forming a pixel electrode on the passivation layer, the pixel electrode being connected to the upper layer through the contact hole.
2. The method of claim 1 , wherein processing the first metal pattern is performed for about 10 seconds.
3. The method of claim 1 , wherein, during removing the first portion of the photoresist pattern, a gas mixture of SF 6 and O 2 is used.
4. The method of claim 3 , wherein the ratio of SF6 to O2 is greater than or equal to 1/20 and less than 1.
5. The method of claim 1 , wherein the upper layer and the lower layer form a data line comprising a source electrode and a drain electrode facing the source electrode, and
the first portion is disposed at a position corresponding to a channel portion between the source electrode and the drain electrode.
6. The method of claim 1 , wherein the first metal layer comprises titanium, and the second metal layer comprises copper.
7. The method of claim 1 , wherein wet etching the second metal layer forms an undercut below the photoresist pattern.
8. The method of claim 1 , wherein forming the lower layer and the ohmic contact is performed by dry etching.
9. A method for manufacturing a thin film transistor array panel, the method comprising:
forming a gate line comprising a gate electrode on a substrate;
forming a gate insulating layer on the gate line;
forming a first amorphous silicon layer, a second amorphous silicon layer, a first metal layer, and a second metal layer on the gate insulating layer;
forming a photoresist pattern having a first portion and a second portion on the second metal layer, the thickness of the second portion being greater than the thickness of the first portion;
forming a second metal pattern and a first metal pattern by respectively etching the second metal layer and the first metal layer using the photoresist pattern as a mask;
forming an amorphous silicon pattern and a semiconductor pattern by respectively etching the second amorphous silicon layer and the first amorphous silicon layer using the photoresist pattern as a mask;
removing the first portion of the photoresist pattern;
forming an upper layer of a data wire by wet etching the second metal pattern using the second portion as a mask;
forming a lower layer of the data wire and an ohmic contact, respectively, by etching the first metal pattern and the amorphous silicon pattern using the second portion as a mask;
forming a passivation layer comprising a contact hole on the upper layer after removing the second portion; and
forming a pixel electrode on the passivation layer, the pixel electrode being connected to the upper layer through the contact hole,
wherein the first portion of the photoresist pattern is removed using a gas mixture of SF 6 and O 2 .
10. The method of claim 9 , wherein the gas mixture has the ratio of SF6 to O2 is greater than or equal to 1/20 and less than 1.
11. The method of claim 9 , wherein the upper layer and the lower layer form a data line comprising a source electrode and a drain electrode facing the source electrode, and
the first portion is disposed at a position corresponding to a channel portion between the source electrode and the drain electrode.
12. The method of claim 9 , wherein the first metal layer comprises titanium, and the second metal layer comprises copper.
13. The method of claim 9 , wherein wet etching the second metal layer forms an undercut below the photoresist pattern.
14. The method of claim 9 , wherein forming the lower layer and the ohmic contact is performed by dry etching.
15. A method for manufacturing a thin film transistor array panel, the method comprising:
forming a gate line comprising a gate electrode on a substrate;
forming a gate insulating layer on the gate line;
forming a first amorphous silicon layer, a second amorphous silicon layer, a first metal layer, and a second metal layer on the gate insulating layer;
forming a photoresist pattern having a first portion and a second portion on the second metal layer, the thickness of the second portion being greater than the thickness of the first portion;
forming a second metal pattern and a first metal pattern by respectively etching the second metal layer and the first metal layer using the photoresist pattern as a mask;
forming an amorphous silicon pattern and a semiconductor pattern by respectively etching the second amorphous silicon layer and the first amorphous silicon layer using the second portion as a mask;
removing the first portion;
cleaning surfaces exposed by removal of the first portion with a gas mixture comprising O 2 and He;
forming an upper layer of a data wire by wet etching the second metal pattern using the second portion as a mask;
forming a lower layer of the data wire and an ohmic contact, respectively, by etching the first metal pattern and amorphous silicon pattern using the second portion as a mask;
forming a passivation layer comprising a contact hole on the upper layer after removing the second portion; and
forming a pixel electrode on the passivation layer, the pixel electrode being connected to the upper layer through the contact hole.
16. The method of claim 15 , wherein cleaning the exposed surfaces injects O 2 at a flow rate ranging from 500 sccm to 15,000 sccm and He at a flow rate of 1000 sccm.
17. The method of claim 15 , further comprising, after forming the first metal pattern, processing the first metal pattern with SF 6 or a gas mixture comprising SF 6 and He.
18. The method of claim 15 , wherein the upper layer and the lower layer form a data line comprising a source electrode and a drain electrode facing the source electrode, and
the first portion is disposed at a position corresponding to a channel portion between the source electrode and the drain electrode.
19. The method of claim 15 , wherein the first metal layer comprises titanium, and the second metal layer comprises copper.
20. The method of claim 15 , wherein wet etching the second metal layer forms an undercut below the photoresist pattern.
21. The method of claim 15 , wherein forming the lower layer and the ohmic contact is performed by dry etching.
22. A method of reducing impurity defects during manufacture of a thin film transistor array panel, the method comprising:
providing a gate line on a substrate, a gate insulating layer on the gate line, at least one silicon-containing layer on the gate insulating layer, at least one metal layer on the at least one silicon-containing layer, and a photoresist pattern on the at least one metal layer;
forming a metal pattern by etching the at least one metal layer using the photoresist pattern as a mask;
subjecting the metal pattern to gas mixture comprising SF 6 ;
forming a silicon-containing pattern by etching the at least one silicon-containing layer using the photoresist pattern as a mask;
removing a first portion of the photoresist pattern;
cleaning surfaces that were exposed by removing the first portion with a gas mixture of SF 6 and O 2 ;
forming a conductive wire by wet etching the metal pattern using a remaining portion of the photoresist pattern as a mask;
forming a semiconductor pattern by etching the silicon-containing pattern using the remaining portion as a mask;
forming a passivation layer comprising a contact hole on the conductive wire after removing the remaining portion; and
forming a pixel electrode on the passivation layer, the pixel electrode being connected to the conductive wire through the contact hole.
23. The method of claim 22 , wherein subjecting the metal pattern is performed for about 10 seconds.
24. The method of claim 22 , wherein, during cleaning, the gas mixture of SF6 and O2 has the ratio of SF6 to O2 is greater than or equal to 1/20 and less than 1.
25. The method of claim 22 , wherein the conductive wire comprises a source electrode and a drain electrode facing the source electrode, and
the first portion is disposed at a position corresponding to a channel portion between the source electrode and the drain electrode.
26. The method of claim 22 , wherein the metal layer comprises a metal selected from titanium and copper.
27. The method of claim 22 , wherein wet etching the metal layer forms an undercut below the photoresist pattern.
28. The method of claim 22 , wherein forming the semiconductor pattern is performed by dry etching.