IP Library Granted Patent US 8,378,748
Granted Patent B2
US 8,378,748 · App. 13/111,423 · Granted Feb 19, 2013

Amplifier

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Quick Facts
Patent No.
US 8,378,748
App. No.
13/111,423
Granted
Feb 19, 2013
Kind
B2
Abstract

The invention relates to a configurable low noise amplifier circuit which is configurable between a first topology in which the low noise amplifier circuit includes a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier, and a second topology in which the low noise amplifier circuit includes a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier.

Claims (48)

1. A configurable low noise amplifier circuit, the low noise amplifier circuit being configurable between one of:

a first topology in which the low noise amplifier circuit comprises a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier; and

a second topology in which the low noise amplifier circuit comprises a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier;

the configurable low noise amplifier further comprising:

a switching arrangement which operatively configures the configurable low noise amplifier circuit between the first topology and the second topology,

wherein when the configurable low noise amplifier circuit is operatively configured in the second topology, the switching arrangement provides an electrical by-pass of the degeneration inductance of the first topology, and

wherein the configurable low noise amplifier circuit further comprises a first switching transistor, the degeneration inductance being operatively coupled in parallel with the first switching transistor.

2. A configurable low noise amplifier circuit according to claim 1 , wherein the low noise amplifier comprises a first input transistor, and the degeneration inductance comprises a degeneration inductor connected between a first output terminal of the first input transistor and ground.

3. A configurable low noise amplifier circuit according to claim 1 , wherein the low noise amplifier comprises a first input transistor, and the feedback resistance comprises a feedback resistor connected between the input terminal of the first input transistor and a first output of the circuit.

4. A configurable low noise amplifier circuit according to claim 3 , wherein the switching arrangement comprises:

a first topology switching function which comprises the first switching transistor connected between a first output terminal of the first input transistor and ground; and

a second topology switching function which comprises a second switching transistor connected between the input terminal of the first input transistor and the feedback resistor,

wherein the circuit is configurable in the first topology by configuring the first and second topology switching functions in an open state, and

wherein the circuit is configurable in the second topology by configuring the first and second topology switching functions in a closed state.

5. A configurable low noise amplifier circuit according to claim 4 ,

wherein each of the switching transistors is configurable in the open state via input of an open state configuration control signal to the input terminal of the respective switching transistor, and

wherein each of the switching transistors is configurable in the closed state via input of a closed state configuration control signal to the input terminal of the respective switching transistor.

6. A configurable low noise amplifier circuit according to claim 2 , the circuit comprising a first cascode transistor connected to a second output terminal of the first input transistor and a first output of the circuit.

7. A configurable low noise amplifier circuit according to claim 4 , the circuit comprising a decoupling capacitor connected between the input terminal of the first input transistor and the second topology switching function.

8. A configurable low noise amplifier circuit according to claim 3 , the circuit comprising a decoupling capacitor connected between the feedback resistor and an output of the circuit.

9. A configurable low noise amplifier circuit according to claim 3 , the circuit comprising a feedback amplifier connected between the feedback resistor and an output of the circuit.

10. A configurable low noise amplifier circuit according to claim 2 , wherein the first topology comprises a capacitor connected between a first output terminal of the first input transistor and ground.

11. A configurable low noise amplifier circuit according to claim 1 , the circuit comprising a configurable load connected to a first output of the circuit.

12. A configurable low noise amplifier circuit according to claim 1 , wherein when the low noise amplifier circuit is configured in the second topology, the degeneration inductance is adapted to provide a power supply noise rejection impedance.

13. A configurable low noise amplifier circuit according to claim 1 , the circuit comprising a second input transistor whereby the low noise amplifier circuit comprises a differential low noise amplifier circuit.

14. A configurable low noise amplifier circuit according to claim 13 , wherein the degeneration inductor comprises a centre-tap differential degeneration inductor connected to a first output terminal of the first input transistor, a first output terminal of the second input transistor and ground.

15. A configurable low noise amplifier circuit according to claim 13 , wherein the feedback resistance comprises a further feedback resistor connected between the input terminal of the second input transistor and a second output of the circuit.

16. A configurable low noise amplifier circuit according to claim 13 , wherein the first topology switching function is connected between the first output terminal of the first input transistor and the first output terminal of the second input transistor, the circuit comprising:

a third topology switching function connected between the input terminal of the second input transistor and the further feedback resistor,

wherein the circuit is configurable in the first topology by configuring the first, second and third topology switching functions in an open state, and

wherein the circuit is configurable in the second topology by configuring the first, second and third topology switching functions in a closed state.

17. A configurable low noise amplifier circuit according to claim 13 , wherein when the low noise amplifier circuit is configured in the second topology, the degeneration inductance is adapted to provide a common-mode signal rejection impedance in relation to signal components common to the first and second input signals.

18. A radio-frequency semiconductor integrated circuit comprising one or more configurable low noise amplifier circuits according to claim 1 .

19. A radio-frequency module comprising one or more radio-frequency filter circuits coupled to one or more configurable low noise amplifier circuits according to claim 1 .

20. A device comprising a configurable low noise amplifier circuit according to claim 1 .

21. A method of configuring a low noise amplifier circuit comprising selectively applying one of:

a first set of one or more control signals to the circuit to configure the circuit in a first topology in which the low noise amplifier circuit comprises a degeneration inductance whereby the low noise amplifier circuit operates as an inductively degenerated low noise amplifier; and

a second set of one or more control signals to the circuit to configure the circuit in a second topology in which the low noise amplifier circuit comprises a feedback resistance whereby the low noise amplifier circuit operates as a resistive feedback low noise amplifier,

wherein when the configurable low noise amplifier circuit is configured in the second topology, a switching arrangement provides an electrical by-pass of the degeneration inductance of the first topology, and

wherein the configurable low noise amplifier circuit further comprises a first switching transistor, the degeneration inductance being operatively coupled in parallel with the first switching transistor.

22. A configurable low noise amplifier circuit, the low noise amplifier circuit being configurable between:

a first internal input impedance matching topology in which the low noise amplifier circuit comprises one or more internal input impedance matching components adapted to match the input impedance of the low noise amplifier to a given input, the one or more internal input impedance matching components being a portion of the low noise amplifier circuit; and

a second topology different from the first internal input impedance matching topology and which comprises a degeneration inductance,

the configurable low noise amplifier circuit further comprising:

a switching arrangement which operatively configures the configurable low noise amplifier circuit between the first internal input matching topology and the second topology,

wherein when the configurable low noise amplifier circuit is configured in the first topology, the switching arrangement provides an electrical by-pass of the degeneration inductance of the second topology, and

wherein the configurable low noise amplifier circuit further comprises a first switching transistor, the degeneration inductance being operatively coupled in parallel with the first switching transistor.

23. A configurable low noise amplifier circuit according to claim 22 , wherein the second topology different from the first internal input impedance matching topology in that the second topology does not include the one or more internal input impedance matching components of the first internal input impedance matching topology.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2014
From: BROADCOM INTERNATIONAL LIMITED
To: BROADCOM CORPORATION
Reel/Frame 032447/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2014
From: RENESAS MOBILE CORPORATION
To: BROADCOM INTERNATIONAL LIMITED
Reel/Frame 032422/0716 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2011
From: HEIKKINEN, JARI JOHANNES; RIEKKI, JONNE JUHANNI; KAUKOVUORI, JOUNI KRISTIAN
To: RENESAS MOBILE CORPORATION
Reel/Frame 026466/0855 →