Multi-transistor exposed conductive clip for high power semiconductor packages
View Patent ↗One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors to implement a buck converter. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors.
1. A high power semiconductor package comprising:
at least two transistors including a control transistor having a control source on a top surface thereof and a sync transistor having a sync drain on a top surface thereof;
a driver integrated circuit (IC) driving said at least two transistors;
an exposed conductive clip coupled to said control source and said sync drain;
a mold compound enclosing said at least two transistors without covering a top surface of said exposed conductive clip.
2. The high power semiconductor package of claim 1 , wherein said driver IC is a flip chip.
3. The high power semiconductor package of claim 2 , wherein said mold compound encloses said driver IC without covering a top surface of said driver IC.
4. The high power semiconductor package of claim 1 , wherein said package comprises a buck converter.
5. The high power semiconductor package of claim 1 , wherein said exposed conductive clip is coupled using solder.
6. The high power semiconductor package of claim 1 , wherein said exposed conductive clip is further attached to a leadframe pad of said package.
7. The high power semiconductor package of claim 1 , wherein said exposed conductive clip comprises a copper clip.
8. The high power semiconductor package of claim 1 , wherein said exposed conductive clip comprises a plurality of stacked clips.
9. The high power semiconductor package of claim 1 , wherein said package is a leadless package.
10. The high power semiconductor package of claim 1 , wherein said at least two transistors include a III-nitride depletion mode transistor.
11. A high power semiconductor package comprising:
a control transistor including a top surface having a control gate and a control source;
a sync transistor including a top surface having a sync drain and a bottom surface including a sync gate;
a driver integrated circuit (IC) coupled to said control gate and said sync gate;
an exposed conductive clip coupled to said control source and said sync drain;
a mold compound enclosing said control transistor and said sync transistor without covering a top surface of said exposed conductive clip.
12. The high power semiconductor package of claim 11 , wherein said driver IC is a flip chip.
13. The high power semiconductor package of claim 12 , wherein said mold compound encloses said driver IC without covering a top surface of said driver IC.
14. The high power semiconductor package of claim 11 , wherein said package comprises a buck converter.
15. The high power semiconductor package of claim 11 , wherein said exposed conductive clip is coupled using solder.
16. The high power semiconductor package of claim 11 , wherein said exposed conductive clip is further attached to a leadframe pad of said package.
17. The high power semiconductor package of claim 11 , wherein said exposed conductive clip comprises a copper clip.
18. The high power semiconductor package of claim 11 , wherein said exposed conductive clip comprises a plurality of stacked clips.
19. The high power semiconductor package of claim 11 , wherein said control transistor is a III-nitride depletion mode transistor.
20. The high power semiconductor package of claim 11 , wherein said sync transistor is a III-nitride depletion mode transistor.