IP Library Granted Patent US 8,570,060
Granted Patent B2
US 8,570,060 · App. 13/111,756 · Granted Oct 29, 2013

Method for protecting a logic circuit against external radiation and associated electronic device

Inventors: Sylvain Clerc (Grenoble, FR); Fabian Firmin (Saint Martin d'Hères, FR); Philippe Roche (Biviers, FR)
Assignee: STMicroelectronics SA
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Quick Facts
Patent No.
US 8,570,060
App. No.
13/111,756
Granted
Oct 29, 2013
Kind
B2
Abstract

A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times.

Claims (28)

1. A method for protecting an electronic circuit against external radiation, the electronic circuit having a first single output, comprising:

duplicating the electronic circuit, wherein the duplicated electronic circuit has a second single output;

configuring the electronic circuit and the duplicated electronic circuit so that the second single output duplicates the first single output at all times;

linking the first single output to first and second inputs of a first combinatorial or sequential element;

linking the second single output to homologous first and second inputs of a second combinatorial or sequential element, wherein the second combinatorial or sequential element is at least functionally identical to the first combinatorial or sequential element; and

linking together respective homologous outputs of the combinatorial or sequential elements.

2. The method according to claim 1 , in which the first and second combinatorial or sequential elements are combinatorial elements and further wherein additional electronic circuits are linked respectively to respective additional inputs of the combinatorial elements.

3. The method according to claim 1 , wherein duplicating the electronic circuit comprises functionally duplicating the electronic circuit.

4. The method according to claim 3 , wherein duplicating the electronic circuit comprises functionally and structurally duplicating the electronic circuit.

5. The method according to claim 1 , wherein duplicating the electronic circuit comprises duplicating the electronic circuit at least twice.

6. The method according to claim 1 , wherein the first and second combinatorial or sequential elements are selected from the group consisting of an inverter and a logic gate and combinations thereof.

7. The method according to claim 6 , wherein the logic gate is selected from the group consisting of a NOR gate and a NAND gate.

8. The method according to claim 1 , wherein the combinatorial or sequential elements are selected from the group consisting of inverters, flip-flops, and latches.

9. An electronic device, comprising:

N functionally identical electronic circuits, each having a single output, wherein N>1, and wherein the outputs of the N functionally identical electronic circuits are configured to be identical at all times;

N functionally identical combinatorial or sequential elements, each having at least two inputs and one output;

each of the single outputs of the electronic circuits being respectively linked to homologous first and second inputs of the combinatorial or sequential elements; and

the homologous outputs of the combinatorial or sequential elements being respectively linked together.

10. The electronic device according to claim 9 , in which N is at least equal to three.

11. The electronic device according to claim 9 , in which the combinatorial or sequential elements comprise PMOS and NMOS transistors whose respective channels exhibit substantially identical dimensional characteristics.

12. The electronic device according to claim 9 , further comprising:

N functionally identical additional electronic circuits, and wherein:

the combinatorial or sequential elements each comprises a respective additional input; and further wherein

respective outputs of the additional electronic circuits are respectively linked to respective homologous additional inputs of the combinatorial or sequential elements.

13. The electronic device according to claim 9 , in which the combinatorial elements comprise CMOS logic gates.

14. The electronic device according to claim 13 , in which the combinatorial elements comprise CMOS inverters.

15. The electronic device according to claim 13 , wherein the N functionally identical electronic circuits are structurally identical.

16. The electronic device according to claim 15 , wherein the N functionally identical combinatorial or sequential elements are structurally identical.

Assignments (2)
CHANGE OF NAME Recorded Dec 8, 2023
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 065835/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2011
From: CLERC, SYLVAIN; FIRMIN, FABIAN; ROCHE, PHILIPPE
To: STMICROELECTRONICS SA
Reel/Frame 026319/0178 →
Priority Claims (1)
FR 10 54032 · May 25, 2010 · national
Continuity (1)
Related Publication 20110291696A1 · Dec 1, 2011