High-side synchronous rectifier circuits and control circuits for power converters
View Patent ↗A control circuit for a switching power converter is provided. The control circuit is installed between a secondary side and an output of the power converter and coupled to control a switching device. The control circuit includes a linear predict circuit, a reset circuit, a charge/discharge circuit, and a PWM circuit. The linear predict circuit is coupled to receive a linear predict signal from the secondary side for generating a charging signal. The reset circuit is couple to receive a resetting signal for generating a discharging signal. The charge/discharge circuit is coupled to receive the charging signal and the discharging signal for generating a ramp signal. The PWM circuit is coupled to receive the linear predict signal for enabling a switching signal and receive the ramp signal for resetting the switching signal.
1. A control circuit for a switching power converter, the control circuit is installed between a secondary side of the switching power converter and an output of the switching power converter and coupled to control a switching device wherein the control circuit comprises:
a linear predict circuit, coupled to receive a linear predict signal from the secondary side for generating a charging signal;
a reset circuit, coupled to receive a resetting signal for generating a discharging signal;
a charge/discharge circuit, coupled to receive the charging signal and the discharging signal for generating a ramp signal; and
a pulse width modulation (PWM) circuit, coupled to receive the linear predict signal for enabling a switching signal and receive the ramp signal for resetting the switching signal:
wherein the linear predict circuit comprises:
a sample-and-hold circuit, coupled to receive the linear predict signal and generate a hold signal in response to the linear predict signal; and
a voltage-to-current converter, coupled to receive the hold signal and generate the charging signal in response to the hold signal.
2. The control circuit as claimed in claim 1 , wherein the reset circuit comprises:
a sample-and-hold circuit, coupled to receive the resetting signal and generate a hold signal in response to the resetting signal; and
a voltage-to-current converter, coupled to receive the hold signal and generate the discharging signal in response to the hold signal.
3. The control circuit as claimed in claim 1 , wherein the charge/discharge circuit comprises:
a capacitor, coupled to receive the charging signal and charged by the charging signal; and
a switch, coupled to the capacitor in series and receiving the discharging signal;
wherein the ramp signal is generated at a joint of the capacitor and the switch in response to the charging signal and the discharging signal.
4. The control circuit as claimed in claim 1 , wherein the PWM circuit comprises:
a SR-flip-flop, coupled to generate the switching signal in response to the linear predict signal and the ramp signal;
a first comparator, coupled to receive the linear predict signal and a first threshold for comparison; and
a second comparator, coupled to receive the ramp signal and a second threshold for comparison;
wherein a setting terminal of the SR-flip-flop is controlled by an output of the first comparator and a resetting terminal of the SR-flip-flop is controlled by an output of the second comparator.
5. A synchronous rectifier circuit for a power converter comprising:
a power switching device, coupled between a secondary side of the power converter and an output of the power converter for rectifying;
a diode, coupled to the power switching device in parallel; and
a control circuit, installed between the secondary side of the power converter and the output of the power converter, wherein the control circuit is operated to receive a linear predict signal and a ramp signal for turning on/off the power switching device;
wherein the control circuit comprises:
a linear predict circuit, coupled to receive the linear predict signal from the secondary side for generating a charging signal;
a reset circuit, coupled to receive a resetting signal for generating a discharging signal;
a charge/discharge circuit, coupled to receive the charging signal and the discharging signal for generating the ramp signal; and
a pulse width modulation (PWM) circuit, coupled to receive the linear predict signal for enabling a switching signal and receive the ramp signal for resetting the switching signal;
wherein the linear predict circuit comprises:
a sample-and-hold circuit, coupled to receive the linear predict signal and generate a hold signal in response to the linear predict signal; and
a voltage-to-current converter, coupled to receive the hold signal and generate the charging signal in response to the hold signal.
6. The synchronous rectifier circuit as claimed in claim 5 , wherein the reset circuit comprises:
a sample and hold circuit, coupled to receive the resetting signal and generate a hold signal in response to the resetting signal; and
a voltage-to-current converter coupled to receive the hold signal and generate the discharging signal in response to the hold signal.
7. The synchronous rectifier circuit as claimed in claim 5 , wherein the charge/discharge circuit comprises:
a capacitor, coupled to receive the charging signal and charged by the charging signal; and
a switch, coupled to the capacitor in series and receiving the discharging signal;
wherein the ramp signal is generated at a joint of the capacitor and the switch in response to the charging signal and the discharging signal.
8. The synchronous rectifier circuit as claimed in claim 5 , wherein the PWM circuit comprises:
a SR-flip-flop, coupled to generate the switching signal in response to the linear predict signal and the ramp signal;
a first comparator, coupled to receive the linear predict signal and a first threshold for comparison;
a second comparator, coupled to receive the ramp signal and a second threshold for comparison;
wherein a setting terminal of the SR-flip-flop is controlled by an output of the first comparator and a resetting terminal of the SR-flip-flop is controlled by an output of the second comparator.