Apparatus for synchronizing a data handover between a first clock domain and a second clock domain through phase synchronization

1. Apparatus for synchronizing a data handover between a first clock domain and a second, different clock domain, the apparatus comprising:

a calculator clocked with a clock of the first clock domain and configured to receive phase information, to provide a synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain, to adjust the synchronization pulse cycle duration information based on the phase information, and to provide a divided clock signal having a frequency substantially equal to half a frequency of the clock of the first clock domain;

a synchronization pulse generator clocked with the clock of the second clock domain and configured to receive the synchronization pulse cycle duration information from the calculator and to generate the synchronization pulse located at the temporal position described by the synchronization pulse cycle duration information;

a phase information provider clocked with the clock of the second clock domain and configured to provide the phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain; and

a feedback path for feeding back the phase information to the calculator; and

a synchronization stage clocked with a clock of the second domain and configured to provide a synchronized version of the divided clock signal synchronized with the second domain, wherein the phase information provider is configured to receive the synchronized version of the divided clock signal.

2. The apparatus according to claim 1 , wherein the calculator is configured to provide the synchronization pulse cycle duration information such that the temporal position of the synchronization pulse is maintained within a predetermined area around a target position defined relative to the clock of the first clock domain.

3. The apparatus according to claim 1 , wherein the calculator is configured to provide the synchronization pulse cycle duration information such that the temporal position of the synchronization pulse is maintained within a predetermined area around a target position, the target position being centered between subsequent clock cycles of the clock of the first clock domain.

4. The apparatus according to claim 1 , wherein the calculator is configured to provide the synchronization pulse cycle duration information such that the synchronization pulse cycle duration information describes the temporal position of the synchronization pulse at the clock of the second clock domain different from a position of the clock of the first clock domain.

5. The apparatus according to claim 1 , wherein the calculator is configured to provide the synchronization pulse cycle duration information such that the synchronization pulse cycle duration information represents a number of clocks in the second clock domain.

6. The apparatus according to claim 5 , further comprising a counter clocked with the clock of the second clock domain and configured to count the clock cycles of the clock in the second clock domain and provide a counter reading based on the count, wherein the synchronization pulse generator is configured to generate the synchronization pulse based on the counter reading such that the synchronization pulse is located at the temporal position described by the number of clock cycles of the clock in the second clock domain that is represented by the synchronization pulse cycle duration information, and wherein the counter reading is set to an initial value in response to the generation of the synchronization pulse.

7. The apparatus according to claim 6 , wherein the synchronization stage comprises a plurality of registers coupled in series and a detector circuit, and wherein the synchronization stage is configured to provide a trigger pulse in synchronization with the second clock domain and in response to a clock edge of the divided clock signal.

8. The apparatus according to claim 7 , wherein the phase information provider comprises a register configured to sample the counter reading in response to the trigger pulse, wherein the feedback path is configured to feed back the sampled counter reading to the calculator.

9. The apparatus according to claim 7 , wherein the apparatus further comprises a register configured to sample a number of clock cycles of the clock in the second clock domain represented by the synchronization pulse cycle duration information in response to the trigger pulse, to thereby accept the synchronization pulse cycle duration information in the second clock domain.

10. The apparatus according to claim 9 , wherein the counter is configured to set the counter reading to the number of clock cycles of the clock in the second clock domain represented by the synchronization pulse cycle duration information and sampled by the register, and is further configured to count down the counter reading from the set counter reading in synchronization with the clock of the second clock domain, and wherein the synchronization pulse generator is configured to compare the counter reading with a predefined number and generate the synchronization pulse when the predefined number is equal to the counter reading.

11. The apparatus according to claim 1 , wherein the calculator is configured to provide the synchronization pulse cycle duration information such that the synchronization pulse cycle duration information describes a number of clock cycles of the clock in the second clock domain, and provide the synchronization pulse cycle duration information such that a mean of the number of clock cycles of the clock in the second clock domain described by a sequence of synchronization pulse cycle duration information items corresponds to a ratio between a frequency of the second clock domain and a frequency of the first clock domain.

12. The apparatus according to claim 1 , wherein the clock of the second clock domain is modulated, wherein the calculator is configured to adjust the synchronization pulse cycle duration information based on modulation data describing a modulation of the clock of the second clock domain.

13. The apparatus according to claim 1 , wherein the calculator comprises a controller configured to regulate the synchronization pulse cycle duration information to bring the phase information towards a predetermined target phase information.

14. The apparatus according to claim 13 , wherein the calculator is configured to combine an output value of the controller with a frequency ratio value describing a frequency ratio between a clock frequency of the second clock domain and a clock frequency of the first clock domain to obtain the synchronization pulse cycle duration information.

15. The apparatus according to claim 1 , further comprising:

a first data processor clocked with the clock of the first clock domain and configured to process an input data such that a data value is provided in synchronization with the first clock domain for handover to the second clock domain; and

a second data processor clocked with the clock of the second clock domain and configured to receive the data value in response to the synchronization pulse, in synchronization with the second clock domain and to process the data value such that an output data is provided in synchronization with the second clock domain.

16. An apparatus for synchronizing a data handover between a first clock domain and a second, different clock domain, the apparatus comprising:

a calculator clocked with a clock of the first clock domain and configured to provide a synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain and to adjust the synchronization pulse cycle duration information based on a phase information, and to provide a divided clock signal;

a synchronization pulse generator clocked with the clock of the second clock domain and configured to receive the synchronization pulse cycle duration information from the calculator and to generate the synchronization pulse located at the temporal position described by the synchronization pulse cycle duration information;

a phase information provider clocked with the clock of the second clock domain and configured to provide the phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain;

a feedback path for feeding back the phase information to the calculator;

a first data processor clocked with the clock of the first clock domain and configured to process an input data such that a reload value and an increment value are provided in synchronization with the first clock domain for handover to the second clock domain;

a second data processor clocked with the clock of the second clock domain and configured to receive the reload value and the increment value in synchronization with the second clock domain and in response to the synchronization pulse, and process the reload value and the increment value such that an output data is provided in synchronization with the second clock domain; and

a synchronization stage clocked with the clock of the second domain and configured to provide a synchronized version of the divided clock synchronized with the second domain, wherein the phase information provider is configured to receive the synchronized version of the divided clock signal.

17. The apparatus according to claim 16 , comprising a counter clocked with the clock of the second clock domain and configured to count clock cycles of the clock in the second clock domain and provide a counter reading, wherein the synchronization pulse generator is configured to generate the synchronization pulse based on the counter reading such that the synchronization pulse is located at the temporal position described by the number of clock cycles in the second clock domain that is represented by the synchronization pulse cycle duration information, and wherein the counter reading is set to an initial value in response to the generation of the synchronization pulse.

18. The apparatus according to claim 17 , further comprising:

a counter clocked with the clock of the second clock domain and configured to count clock cycles of the clock in the second clock domain and provide a counter reading, wherein the synchronization pulse generator is configured to generate the synchronization pulse based on the counter reading such that the synchronization pulse is located at the time position defined by the number of clock cycles of the clock in the second clock domain, and wherein the counter reading is reset upon generation of the synchronization pulse.

19. The apparatus according to claim 16 , wherein the second data processor comprises an integrator configured to provide the reload value as output data in response to the synchronization pulse and increment the previous output data by the increment value at each subsequent clock cycle of the clock of the second clock domain.

20. An apparatus for synchronizing a data handover between a first clock domain and a second, different clock domain, the apparatus comprising:

a means for receiving a phase information, providing a synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain and providing a divided clock signal having a frequency substantially equal to half a frequency of a clock of the of the first clock domain, wherein the means for providing the synchronization pulse cycle duration information is clocked with the clock of the first clock domain, and adjusting the synchronization pulse cycle duration information based on the phase information;

a means for generating the synchronization pulse such that the synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information, wherein the means for generating the synchronization pulse is clocked with the clock of the second clock domain;

a means for providing a phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain, wherein the means for providing the phase information is clocked with the clock of the second clock domain; and

a means for feeding back the phase information to the means for receiving the phase information; and

a means for providing a synchronized version of the divided clock signal synchronized with the second domain, wherein the means for providing the phase information is configured to receive the synchronized version of the divided clock signal.

21. A method for synchronizing a data handover between a first clock domain and a second, different clock domain, the method comprising:

providing in the first clock domain a synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain;

providing a divided clock signal having a frequency substantially equal to half a frequency of a clock of the first clock domain;

providing a synchronized version of the divided clock signal, wherein the synchronized version is synchronized with the second domain;

generating in the second clock domain the synchronization pulse located at the temporal position described by the synchronization pulse cycle duration information;

providing in the second clock domain a phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain;

feeding back the phase information to the first clock domain; and

adjusting the synchronization pulse cycle duration information based on the phase information.

22. The method according to claim 21 , wherein the synchronization pulse cycle duration information represents, in the form of coded numeric value, a number of clock cycles of the clock in the second clock domain.

23. The method according to claim 22 , comprising counting in response to clock cycles of the clock of the second clock domain and providing a counter reading, wherein the synchronization pulse is generated based on the counter reading such that a temporal position of the synchronization pulse is adjusted based on the synchronization pulse cycle duration information, and wherein the counter reading is set to an initial value in response to a generation of the synchronization pulse.

24. The method according to claim 21 , further comprising:

processing an input data such that a data value is provided in synchronization with the first clock domain for handover to the second clock domain;

receiving the data value in synchronization with the second clock domain and in response to the synchronization pulse; and

processing the data value such that an output data is provided in synchronization with the second clock domain.

25. A computer readable digital, non-transitory storage medium having stored thereon a computer program having a program code for performing, when running on a computer, a method for synchronizing a data handover between a first clock domain and a second clock domain, the method comprising:

providing in the first clock domain a synchronization pulse cycle duration information describing a temporal position of a synchronization pulse to be generated at a clock of the second clock domain;

providing in the first clock domain, a divided clock signal having a frequency substantially equal to half a frequency of a clock of the first domain;

providing in the second clock domain, a synchronized version of the divided clock synchronized with the second clock domain;

generating in the second clock domain the synchronization pulse located at the temporal position described by the synchronization pulse cycle duration information;

providing in the second clock domain a phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain;

feeding back the phase information to the first clock domain; and

adjusting the synchronization pulse cycle duration information based on the phase information.