Semiconductor integrated circuit device having improved interconnect accuracy near cell boundaries
A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.
1. A semiconductor integrated circuit device comprising:
first and second standard cells that are different in cell structure from each other and placed adjacent to each other along a cell boundary extending in a first direction,
wherein in the first and second standard cells:
first metal interconnect regions, which extend in the first direction wherein no other metal interconnect region exists between the first metal interconnect regions and the cell boundary, are placed to have a substantially same distance from the cell boundary in a second direction perpendicular to the first direction,
diffusion regions, from which to the cell boundary no other diffusion region exists, are asymmetric with respect to the cell boundary, and
the first metal interconnect regions are dummy patterns.
2. The semiconductor integrated circuit device of claim 1 ,
wherein in the first and second standard cells:
second metal interconnect regions, which extend in the first direction wherein no other metal interconnect region exists between the second metal interconnect regions and the cell boundary, are placed at a first predetermined distance from the cell boundary in the second direction, and
the first predetermined distance is substantially the same as the distance between the first metal interconnect regions and the cell boundary.
3. The semiconductor integrated circuit device of claim 2 , wherein at least one of the second metal interconnect regions is connected to a power supply line or a ground line.
4. The semiconductor integrated circuit device of claim 2 , wherein at least one of the second metal interconnect regions is a pattern.
5. The semiconductor integrated circuit device of claim 2 , wherein at least one of the first metal interconnect regions and the second metal interconnect regions is disposed over a diffusion region of the diffusion regions.
6. The semiconductor integrated circuit device of claim 2 , wherein contacts, which are provided above the second metal interconnect regions in the first and second standard cells, are asymmetric with respect to the cell boundary.
7. The semiconductor integrated circuit device of claim 2 ,
wherein in at least one of the first and second standard cells,
a third metal interconnect region, which extends in the first direction wherein no other metal interconnect region exists between the third metal interconnect region and the cell boundary, is placed at the first predetermined distance from the cell boundary in the second direction.
8. The semiconductor integrated circuit device of claim 7 , wherein the third metal interconnect region is a dummy pattern.
9. The semiconductor integrated circuit device of claim 7 , wherein the third metal interconnect region is a pattern.
10. The semiconductor integrated circuit device of claim 2 , wherein
in the first and second standard cells,
the first metal interconnect regions and the second interconnect regions are placed at a second predetermined distance from each other in the first direction.
11. The semiconductor integrated circuit device of claim 10 ,
wherein in at least one of the first and second standard cells,
a third metal interconnect region, which extends in the first direction wherein no other metal interconnect region exists between the third metal interconnect region and the cell boundary, is placed at the first predetermined distance from the cell boundary in the second direction,
the third metal interconnect region is placed at the second predetermined distance from either one of the first interconnect regions and the second interconnect regions in the first direction without overlapping with the first interconnect regions and the second interconnect regions.
12. The semiconductor integrated circuit device of claim 10 , wherein the second predetermined distance is a distance which can be substantially regarded as non-existent from a standpoint of an optical proximity effect.
13. The semiconductor integrated circuit device of claim 7 , wherein each of the first metal interconnect regions, the second metal interconnect regions and the third metal interconnect region is rectangular.
14. The semiconductor integrated circuit device of claim 2 , wherein in the second metal interconnect regions, positions of contacts are different in the second direction.
15. The semiconductor integrated circuit device of claim 7 , wherein
in at least one of the first and second standard cells,
each of the first metal interconnect regions, the second metal interconnect regions and the third metal interconnect region is disposed in a same metal interconnect layer.
16. The semiconductor integrated circuit device of claim 15 ,
wherein in at least one of the first and second standard cells,
a power supply line and a ground line are disposed in the same metal interconnect layer.