Vertical power MOSFET and IGBT fabrication process with two fewer photomasks

1. A process for fabrication of a power semiconductor device, comprising:

depositing a single photomask on a layer of polysilicon on a wafer;

removing the polysilicon layer from first regions of the power semiconductor device where p-conductivity type well regions and n-conductivity type source regions are to be formed;

introducing a p-conductivity type dopant into the wafer through the first regions to form the p-conductivity type well regions;

removing the single photomask;

introducing an n-conductivity type dopant into the wafer through the first regions to form the n-conductivity type source regions;

forming a multipurpose photomask on the wafer to overlie regions of the polysilicon layer which remain on the wafer, the polysilicon layer having an upper surface and having sidewalls, the multipurpose photomask overlying both the upper surface and the sidewalls, but leaving portions of the wafer exposed between the sidewalls;

implanting p-conductivity type impurity through the portions of the wafer exposed between the sidewalls to form p-conductivity type impurity regions within the p-conductivity type well regions; and

etching the wafer at locations where the portions of the wafer are exposed between the sidewalls to form recesses reaching toward the p-conductivity type impurity regions, wherein the etching of the wafer occurs after the implanting of the p-conductivity type impurity.

2. The process of claim 1 , further comprising:

depositing a layer of insulating material over the surface of the wafer; and

depositing a layer of metal over the layer of insulating material.

3. The process of claim 2 , further comprising:

etching metal to define electrical contacts to the power semiconductor device.

4. The process of claim 3 , wherein the power semiconductor device is a vertical power MOSFET.

5. The process of claim 3 , wherein the power semiconductor device is an insulated gate bipolar transistor.

6. The process of claim 1 , wherein the process for fabrication of the power semiconductor device involves no more than four photomasks.

7. A process for making a power semiconductor device comprising:

on a substrate comprising an n-conductivity type semiconductor, forming a layer of gate oxide;

introducing n-conductivity type dopant into the substrate through the gate oxide;

depositing a layer of polycrystalline silicon on the gate oxide;

masking the layer of polycrystalline silicon to define first locations for introduction of impurities;

implanting p-conductivity type impurity into the first locations to provide p-wells in the substrate;

implanting n-conductivity type impurity into the first locations to provide source regions;

providing a masking layer over an upper surface of the layer of polycrystalline silicon and over exposed sidewalls of the layer of polycrystalline silicon to thereby define second locations within the first locations;

introducing p-conductivity type impurity into the second locations to form p-conductivity type impurity regions within the p-wells; and

performing a shallow etch of the substrate through the second locations to form recesses reaching toward the p-conductivity type impurity regions within the p-wells, wherein the performing of the shallow etch of the substrate occurs after the introducing the p-conductivity type impurity into the second locations.

8. The process of claim 7 , further including:

depositing a layer of insulating material over the layer of polysilicon; and

annealing the layer of insulating material to cause smoothing of the layer of insulating material and diffusion of the n-conductivity type and p-conductivity type impurities into the substrate.

9. The process of claim 7 , further comprising providing metal connections to the recesses reaching toward the p-conductivity type impurity regions within the p-wells.

10. The process of claim 9 , wherein the power semiconductor device is a vertical power MOSFET.

11. The process of claim 9 , wherein the power semiconductor device is an insulated gate bipolar transistor.

12. The process of claim 7 , wherein the process for making the power semiconductor device involves no more than four photomasks.

13. A method of manufacturing a power semiconductor device comprising:

(a) forming a layer of gate oxide on a substrate, wherein the substrate comprises an n-conductivity type semiconductor;

(b) implanting an n-conductivity type dopant into the substrate through the gate oxide;

(c) depositing a layer of polycrystalline silicon onto the gate oxide;

(d) depositing a first layer of photoresist onto the layer of polycrystalline silicon thereby defining a plurality of exposed regions;

(e) etching the layer of polycrystalline silicon at each of the plurality of exposed regions;

(f) implanting a p-conductivity type dopant into the plurality of exposed regions;

(g) etching the first layer of photoresist deposited in (d);

(h) heating the substrate to drive the p-conductivity type dopant deeper into the substrate thereby forming a plurality of p-conductivity type wells;

(i) implanting an n-conductivity type dopant into the p-conductivity type wells:

(j) depositing a second layer of photoresist onto the layer of polycrystalline silicon and portions of the substrate, wherein the layer of polycrystalline silicon has an upper surface and a plurality of sidewalls, and wherein the second layer of photoresist overlies both the upper surface and the sidewalls, and wherein portions of the substrate between the sidewalls that are exposed through the second layer of photoresist;

(k) implanting p-conductivity type dopant through the portions of the substrate between the sidewalls that are exposed through the second layer of photoresist to form p-conductivity type dopant regions; and

(l) etching the portions of the substrate between the sidewalls that are exposed through the second layer of photoresist to form recesses reaching toward the p-conductivity type dopant regions, wherein the etching of the substrate of (l) occurs after the implanting of the p-conductivity type dopant of (k).

14. The method of claim 13 , further comprising:

(m) depositing a layer of insulating material onto the layer of polycrystalline silicon and portions of the substrate; and

(n) depositing a layer of metal over the layer of insulating material.

15. The method of claim 14 , further comprising:

(o) etching the layer of metal deposited in (n) to define electrical contacts to the power semiconductor device.

16. The method of claim 13 , wherein the depositing of the first layer of photoresist in (d) forms a photomask, and wherein the power semiconductor device is manufactured using no more than four photomasks.

17. The method of claim 13 , wherein the power semiconductor device is an Insulated Gate Bipolar Transistor (IGBT).

18. The method of claim 13 , wherein the power semiconductor device is a vertical power Metal Oxide Semiconductor Field Effect Transistor (MOSFET).