Entropy decoding methods and apparatus using most probable and least probable signal cases
View Patent ↗An entropy decoding apparatus may include a data structure stored in memory. The data structure may include a decoding engine vector or context engine vector. The decoding engine vector many have a first set of bits representing a value corresponding to a state of a coding engine, a second set of bits representing an offset value, and a third set of bits representing the contents of an input stream buffer. The context vector may have a first set of bits representing an addresses of a context most probable state, a second set of bits representing a plurality of possible values corresponding to a least probable symbol state of a coding engine, a third set of bits representing an addresses of a context least probable state, a fourth set of bits representing a binary most probable symbol value, and a fifth set of bits representing a binary least probable symbol value.
1. An apparatus for entropy decoding, comprising:
a processor module;
a memory coupled to the processor module; and
a data structure stored in the memory, the data structure including a context vector having:
a first set of bits representing an addresses of a context most probable state,
a second set of bits representing a plurality of possible values corresponding to a least probable symbol state of a coding engine,
a third set of bits representing an addresses of a context least probable state,
a fourth set of bits representing a binary most probable symbol value; and
a fifth set of bits representing a binary least probable symbol value.
2. The apparatus of claim 1 wherein the second set of bits represents four possible values.
3. The apparatus of claim 1 wherein the first and/or third set of bits includes a subset of bits represents an index that points to an address of a new context, wherein the index includes a bit indicating a binary most probable symbol value for the new context.
4. The apparatus of claim 1 wherein the data structure further includes a decoding engine vector having:
a first set of bits representing a value corresponding to a state of a coding engine,
a second set of bits representing an offset value; and
a third set of bits representing the contents of an input stream buffer.
5. The apparatus of claim 4 wherein a total number of bits in the first, second and third sets of bits equals a maximum number of bits that can fit in one or more registers of the processor module.
6. The apparatus of claim 5 wherein the processor module includes a single instruction multiple data (SIMD) processor.
7. A non-transitory processor readable medium having embodied therein a processor readable data structure for entropy decoding, the data structure the data structure including a context vector having:
a first set of bits representing an addresses of a context most probable state,
a second set of bits representing a plurality of possible values corresponding to a least probable symbol state of a coding engine,
a third set of bits representing an addresses of a context least probable state,
a fourth set of bits representing a binary most probable symbol value; and
a fifth set of bits representing a binary least probable symbol value.
8. The non-transitory processor readable medium of claim 7 wherein the second set of bits represents four possible values.
9. The non-transitory processor readable medium of claim 7 wherein the first and/or third set of bits includes a subset of bits that represents an index that points to an address of a new context, wherein the index includes a bit indicating a binary most probable symbol value for the new context.