Octal serial gigabit media-independent interface

1. A method comprising, by one or more computer systems:

receiving, from a single chip, eight parallel data streams having a first data rate;

multiplexing by round-robin selection the eight parallel data streams into a single multiplexed data stream having the eight parallel data streams;

maintaining DC bias on the multiplexed data stream having the eight parallel data streams by encoding the multiplexed data stream having the eight parallel data streams using a single self-synchronous scrambler;

serializing the modified multiplexed data stream, by a single serializer/deserializer chip, into a serial data stream having a second data rate that is approximately equal to ten times the first data rate; and

transmitting to a receiver the modified serial data stream at the second data rate.

2. The method of claim 1 , wherein the parallel data streams comprise a 10-bit data width encoding eight-bit symbols.

3. The method of claim 1 , wherein the transmitter is in a media-access control chip and transmits to a PHY chip that interfaces with a physical transmission medium.

4. The method of claim 1 , wherein the transmitter is in a PHY chip that interfaces with a physical transmission medium, and transmits to a media-access control chip.

5. The method of claim 1 , wherein the second data rate is approximately equal to 10.3125 times the first data rate.

6. A method comprising, by one or more computer systems:

receiving, from a single chip, eight parallel data streams having a first data rate;

multiplexing by round-robin selection the eight parallel data streams into a first single multiplexed data stream having the eight parallel data streams;

maintaining DC bias on the multiplexed data stream having the eight parallel data streams by encoding the multiplexed data stream having the eight parallel data streams using a single self-synchronous scrambler;

serializing the modified multiplexed data stream, by a single serializer/deserializer chip, into a serial data stream having a second data rate that is approximately equal to ten times the first data rate;

transmitting to a receiver the serial data stream at the second data rate;

receiving, at the receiver coupled to a transmitter, the serial data stream;

de-serializing, by a single serializer/deserializer chip, the serial data stream into a second single multiplexed data stream;

de-multiplexing, through a de-multiplexer, the second single multiplexed data stream into eight received parallel data streams; and

decoding each of said eight received parallel data streams.

7. The method of claim 6 , wherein the parallel data streams comprise a 10-bit data width encoding eight bit symbols.

8. The method of claim 6 , wherein the receiver is in a media-access control chip and receives from a PHY chip that interfaces with a physical transmission medium.

9. The method of claim 6 , wherein the receiver is in a PHY chip that interfaces with a physical transmission medium, and receives from a media-access control chip.

10. One or more computer-readable non-transitory storage media embodying software that is operable when executed to:

receive, from a single chip, eight parallel data streams having a first data rate;

multiplex by round-robin selection the eight parallel data streams into a single multiplexed data stream having the eight parallel data streams;

maintain DC bias on the multiplexed data stream having the eight parallel data streams by encoding the multiplexed data stream having the eight parallel data streams using a single self-synchronous scrambler;

serialize the modified multiplexed data stream, by a single serializer/deserializer chip, into a serial data stream having a second data rate that is approximately equal to ten times the first data rate; and

transmit to a receiver the modified serial data stream at the second data rate.

11. The media of claim 10 , wherein the parallel data streams comprise a 10-bit data width encoding eight-bit symbols.

12. The media of claim 10 , wherein the transmitter is in a media-access control chip and transmits to a PHY chip that interfaces with a physical transmission medium.

13. The media of claim 10 , wherein the receiver is in a PHY chip that interfaces with a physical transmission medium, and transmits to a media-access control chip.

14. The media of claim 10 , wherein the second data rate is approximately equal to 10.3125 times the first data rate.

15. One or more computer-readable non-transitory storage media embodying software that is operable when executed to:

receive, from a single chip, eight parallel data streams having a first data rate;

multiplex by round-robin selection the eight parallel data streams into a first single multiplexed data stream having the eight parallel data streams;

maintain DC bias on the multiplexed data stream having the eight parallel data streams by encoding the multiplexed data stream having the eight parallel data streams using a single self-synchronous scrambler;

serialize the modified multiplexed data stream, by a single serializer/deserializer chip, into a serial data stream having a second data rate that is approximately equal to ten times the first data rate;

transmit to a receiver the serial data stream at the second data rate;

receive, at the receiver coupled to a transmitter, the serial data stream;

de-serialize, by a single serializer/deserializer chip, the serial data stream into a second single multiplexed data stream;

de-multiplex, through a de-multiplexer, the second single multiplexed data stream into eight received parallel data streams; and

decode each of said eight received parallel data streams.

16. The media of claim 15 , wherein the parallel data streams comprise a 10-bit data width encoding eight bit symbols.

17. The media of claim 15 , wherein the receiver is in a media-access control chip and receives from a PHY chip that interfaces with a physical transmission medium.

18. The media of claim 15 , wherein the receiver is in a PHY chip that interfaces with a physical transmission medium, and receives from a media-access control chip.

19. A system comprising:

means for receiving, from a single chip, eight parallel data streams having a first data rate;

means for multiplexing by round-robin selection the eight parallel data streams into a single multiplexed data stream having the eight parallel data streams;

means for maintaining DC bias on the multiplexed data stream having the eight parallel data streams by encoding the multiplexed data stream having the eight parallel data streams using a single self-synchronous scrambler;

means for serializing the modified multiplexed data stream, by a single serializer/deserializer chip, into a serial data stream having a second data rate that is approximately equal to ten times the first data rate; and

means for transmitting to a receiver the modified serial data stream at the second data rate.

20. The system of claim 19 , wherein the parallel data streams comprise a 10-bit data width encoding eight-bit symbols.

21. The system of claim 19 , wherein the means for transmitting is in a media-access control chip and transmits to a PHY chip that interfaces with a physical transmission medium.

22. The system of claim 19 , wherein the means for transmitting is in a PHY chip that interfaces with a physical transmission medium, and transmits to a media-access control chip.

23. The system of claim 19 , wherein the second data rate is approximately equal to 10.3125 times the first data rate.

24. A system comprising:

means for receiving, from a single chip, eight parallel data streams having a first data rate;

means for multiplexing by round-robin selection the eight parallel data streams into a first single multiplexed data stream having the eight parallel data streams;

means for maintaining DC bias on the multiplexed data stream having the eight parallel data streams by encoding the multiplexed data stream having the eight parallel data streams using a single self-synchronous scrambler;

means for serializing the modified multiplexed data stream, by a single serializer/deserializer chip, into a serial data stream having a second data rate that is approximately equal to ten times the first data rate;

means for transmitting to a receiver the serial data stream at the second data rate;

means for receiving, at the receiver coupled to a transmitter, the serial data stream;

means for de-serializing, by a single serializer/deserializer chip, the serial data stream into a second single multiplexed data stream;

means for de-multiplexing, through a de-multiplexer, the second single multiplexed data stream into eight received parallel data streams; and

means for decoding each of said eight received parallel data streams.

25. The system of claim 24 , wherein the parallel data streams comprise a 10-bit data width encoding eight bit symbols.

26. The system of claim 24 , wherein the means for receiving is in a media-access control chip and receives from a PHY chip that interfaces with a physical transmission medium.

27. The system of claim 24 , wherein the means for receiving is in a PHY chip that interfaces with a physical transmission medium, and receives from a media-access control chip.