Thin film transistor array substrate and method of fabricating the same
View Patent ↗A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.
1. A thin film transistor array substrate, comprising:
a gate electrode disposed on a substrate;
a gate insulating film disposed on the substrate;
an oxide semiconductor pattern disposed on the gate insulating film;
an anti-etching pattern disposed on the oxide semiconductor pattern;
a source electrode and a drain electrode disposed on the anti-etching pattern;
a passivation film disposed on the anti-etching pattern, the source electrode, and the drain electrode; and
a column spacer formed through the gate insulating film,
wherein the oxide semiconductor pattern comprises an edge portion,
wherein the edge portion comprises a conductive region and a non-conductive region, and
wherein the column spacer overlaps at least a portion of the non-conductive region.
2. The thin film transistor array substrate of claim 1 , wherein the column spacer comprises:
a first sidewall in contact with the passivation film, the anti-etching pattern, the oxide semiconductor pattern, and the gate insulating film; and
a second sidewall in contact with the passivation film and the gate insulating film.
3. The thin film transistor array substrate of claim 1 , wherein a portion of a sidewall of the anti-etching pattern of the conductive region is formed to protrude from a sidewall of the oxide semiconductor pattern, and at least a portion of a sidewall of the anti-etching pattern of the non-conductive region is arranged vertically with a sidewall of the oxide semiconductor pattern.
4. The thin film transistor array substrate of claim 1 , wherein
the non-conductive region comprises a first non-conductive region and a second non-conductive region;
the column spacer comprises a first column spacer and a second column spacer;
the gate electrode comprises a gate electrode opening; and
at least one of the non-conductive regions and at least one of the column spacer are formed in the gate electrode opening.
5. The thin film transistor array substrate of claim 4 , wherein the anti-etching pattern disposed on the first non-conductive region not arranged within the gate electrode opening has a first width and the anti-etching pattern disposed on the second non-conductive region arranged within the gate electrode opening has a second width smaller than the first width.
6. The thin film transistor array substrate of claim 1 , wherein the anti-etching pattern comprises:
a first region in which the anti-etching pattern overlaps the gate electrode; and
a second region in which the anti-etching pattern does not overlap the gate electrode, and
wherein the first region of the anti-etching pattern has a first width and the second region of the anti-etching pattern has a second width smaller than the first width.
7. A thin film transistor array substrate, comprising:
a gate electrode disposed on a substrate;
a gate insulating film disposed on the substrate;
an oxide semiconductor pattern disposed on the gate insulating film;
an anti-etching pattern disposed on the oxide semiconductor pattern;
a passivation film disposed on the anti-etching pattern, a source electrode, and a drain electrode; and
a column spacer formed through the passivation film and the gate insulating film,
wherein the column spacer overlaps at least a portion of a non-conductive region of the oxide semiconductor pattern,
wherein the column spacer comprises a first sidewall in contact with the passivation film,
the anti-etching pattern, the oxide semiconductor pattern, and the gate insulating film, and a second sidewall in contact with the passivation film and the gate insulating film.
8. The thin film transistor array substrate of claim 7 , wherein the oxide semiconductor pattern comprises an edge portion along an edge of the oxide semiconductor pattern, and the edge portion comprises a conductive region and a non-conductive region.
9. The thin film transistor array substrate of claim 8 , wherein the conductive region comprises a region in contact with the column spacer.
10. The thin film transistor array substrate of claim 7 , wherein the passivation film, the anti-etching pattern, and the oxide semiconductor pattern are arranged vertically along the first sidewall of the column spacer.
11. The thin film transistor array substrate of claim 7 , wherein the column spacer comprises an upper region and a lower region, and
wherein a distance between the first sidewall and the second sidewall in the upper region is larger than a distance between the first sidewall and the second sidewall in the lower region.
12. The thin film transistor array substrate of claim 11 , wherein the upper region of the column spacer does not overlap with the gate electrode.
13. The thin film transistor array substrate of claim 7 , wherein the column spacer overlaps at least a portion of the passivation film.
14. The thin film transistor array substrate of claim 7 , wherein the column spacer comprises a transparent organic material or a light blocking material.
15. The thin film transistor array substrate of claim 7 , wherein the anti-etching pattern comprises a first region in which the anti-etching pattern overlaps the gate electrode and a second region in which the anti-etching pattern does not overlap with the gate electrode.