Memory storage device having a variable resistance memory storage element
View Patent ↗A memory storage device includes: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.
1. A memory storage device comprising:
a lower electrode on a plug layer;
a memory storage layer on the lower electrode, the memory storage layer configured to record information by way of a change in resistance; and
an upper electrode on the memory storage layer,
wherein,
(a) the lower electrode includes
(1) a first layer which comprises of metal or metal silicide and
(2) a second layer on the first layer, the second layer comprises of a metal nitride, and
(b) the first layer and the second layer are laminated such that only the first layer is in contact with the plug layer and only the second layer is in contact with the memory storage layer.
2. A memory storage device according to claim 1 , wherein the metal of the first layer is formed of one or more kinds selected out of Ti, Co, Ni, W, and Ta.
3. A memory storage device according to claim 1 , wherein the plug layer comprises _polysilicon.
4. A memory storage device comprising:
a lower electrode;
a memory storage layer on the lower electrode, the memory storage layer configured to record information by way of a change in resistance;
an upper electrode on the memory storage layer; and
a plug layer under the lower electrode,
wherein,
the lower electrode includes a metal silicide layer.
5. The memory storage device according to claim 1 wherein the memory storage layer and the upper electrode are common to a memory cell.
6. The memory storage device according to claim 1 wherein the lower electrode and the memory cell are separate from each other.
7. The memory storage device according to claim 4 wherein the memory storage layer and the upper electrode are common to a memory cell.
8. The memory storage device according to claim 4 wherein the lower electrode and the memory cell are separate from each other.
9. The memory storage device according to claim 4 wherein the plug layer comprises polysilicon.